PDF AD9142A Data sheet ( Hoja de datos )

Número de pieza	AD9142A
Descripción	Digital-to-Analog Converter
Fabricantes	Analog Devices
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Data Sheet Dual, 16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter AD9142A FEATURES Supports input data rate up to 575 MHz Very small inherent latency variation: <2 DAC clock cycles Proprietary low spurious and distortion design 6-carrier GSM ACLR = 79 dBc at 200 MHz IF SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF Flexible 16-bit LVDS interface Supports word and byte load Data interface DLL Sample error detection and parity Multiple chip synchronization Fixed latency and data generator latency compensation Selectable 2×, 4×, 8× interpolation filter Low power architecture fS/4 power saving coarse mixer Input signal power detection Emergency stop for downstream analog circuitry protection FIFO error detection On-chip numeric control oscillator allows carrier placement anywhere in the DAC Nyquist bandwidth Transmit enable function for extra power saving High performance, low noise PLL clock multiplier Digital gain and phase adjustment for sideband suppression Digital inverse sinc filter Low power: 1.8 W at 1.6 GSPS, 1.5 W at 1.25 GSPS, full operating conditions 72-lead LFCSP APPLICATIONS Wireless communications: 3G/4G and MC-GSM base stations, wideband repeaters, software defined radios Wideband communications: point-to-point, LMDS/MMDS Transmit diversity/MIMO Instrumentation Automated test equipment GENERAL DESCRIPTION The AD9142A is a dual, 16-bit, high dynamic range digital-to- analog converter (DAC) that provides a sample rate of 1600 MSPS, permitting a multicarrier generation up to the Nyquist frequency. The AD9142A TxDAC+® includes features optimized for direct conversion transmit applications, including complex digital mod- ulation, input signal power detection, and gain, phase, and offset compensation. The DAC outputs are optimized to interface seam- lessly with analog quadrature modulators, such as the ADL537x F-MOD series and the ADRF670x series from Analog Devices, Inc. A 3-wire serial port interface provides for the programming/ readback of many internal parameters. Full-scale output current can be programmed over a range of 9 mA to 33 mA. The AD9142A is available in a 72-lead LFCSP. PRODUCT HIGHLIGHTS 1. Wide signal bandwidth (BW) enables emerging wideband and multiband wireless applications. 2. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. 3. Very small inherent latency variation simplifies both software and hardware design in the system. It allows easy multichip synchronization for most applications. 4. New low power architecture improves power efficiency (mW/MHz/channel) by 30%. 5. Input signal power and FIFO error detection simplify designs for downstream analog circuitry protection. 6. Programmable transmit enable function allows easy design balance between power consumption and wakeup time. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page AD9142A REVISION HISTORY 5/14—Rev. 0 to Rev. A Change to Table 25 ......................................................................... 51 Changes to Table 103...................................................................... 69 12/13—Revision 0: Initial Version Data Sheet Rev. A \| Page 4 of 72 5 Page AD9142A Data Sheet AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 5. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 737.28 MSPS BW = 125 MHz BW = 270 MHz fDAC = 983.04 MSPS BW = 360 MHz fDAC = 1228.8 MSPS BW = 200 MHz BW = 500 MHz fDAC = 1474.56 MSPS BW = 737 MHz BW = 400 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 737.28 MSPS fDAC = 983.04 MSPS fDAC = 1228.8 MSPS fDAC = 1474.56 MSPS NOISE SPECTRAL DENSITY (NSD) fDAC = 737.28 MSPS fDAC = 983.04 MSPS fDAC = 1228.8 MSPS fDAC = 1474.56 MSPS W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR) fDAC = 983.04 MSPS fDAC = 1228.8 MSPS fDAC = 1474.56 MSPS W-CDMA SECOND (ACLR) fDAC = 983.04 MSPS fDAC = 1228.8 MSPS fDAC = 1474.56 MSPS Test Conditions/Comments −14 dBFS single tone fOUT = 200 MHz fOUT = 200 MHz fOUT = 280 MHz fOUT = 10 MHz fOUT = 280 MHz −12 dBFS each tone fOUT = 200 MHz fOUT = 200 MHz fOUT = 280 MHz fOUT = 10 MHz fOUT = 280 MHz Eight-tone, 500 kHz tone spacing fOUT = 200 MHz fOUT = 200 MHz fOUT = 280 MHz fOUT = 10 MHz fOUT = 280 MHz Single carrier fOUT = 200 MHz fOUT = 20 MHz fOUT = 280 MHz fOUT = 20 MHz fOUT = 280 MHz Single carrier fOUT = 200 MHz fOUT = 20 MHz fOUT = 280 MHz fOUT = 20 MHz fOUT = 280 MHz Min Typ Max Unit 85 80 85 85 75 85 80 80 82 80 85 79 −160 −161.5 −164.5 −166 −162.5 81 83 80 81 80 85 86 86 86 85 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc OPERATING SPEED SPECIFICATIONS Table 6. Interpolation Factor 2× 4× 8× DVDD18, CVDD18 = 1.8 V ± 5% fDCI (MSPS) Maximum fDAC (MSPS) Maximum 575 1150 350 1400 175 1400 DVDD18, CVDD18 = 1.9 V ± 5% or 1.8 V ± 2% fDCI (MSPS) Maximum fDAC (MSPS) Maximum 575 1150 375 1500 187.5 1500 DVDD18, CVDD18 = 1.9 V ± 2% fDCI (MSPS) Maximum fDAC (MSPS) Maximum 575 1150 400 1600 200 1600 Rev. A \| Page 10 of 72 11 Page

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