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PDF AD9164 Data sheet ( Hoja de datos )
| Número de pieza | AD9164 | |
| Descripción | RF DAC and Direct Digital Synthesizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
16-Bit, 12 GSPS,
RF DAC and Direct Digital Synthesizer
AD9164
FEATURES
fast hop modes, phase coherent fast frequency hopping (FFH) is
DAC update rate up to 12 GSPS (minimum)
enabled, with several modes to support multiple applications.
Direct RF synthesis at 6 GSPS (minimum)
In baseband mode, wide analog bandwidth capability combines
DC to 2.5 GHz in baseband mode
with high dynamic range to support DOCSIS 3.1 cable infrastruc-
DC to 6 GHz in 2× nonreturn-to-zero (NRZ) mode
ture compliance from the minimum of one carrier up to the full
1.5 GHz to 7.5 GHz in Mix-Mode
maximum spectrum of 1.791 GHz of signal bandwidth. A 2×
Bypassable interpolation
interpolator filter (FIR85) enables the AD9164 to be configured
2×, 3×, 4×, 6×, 8×, 12×, 16×, 24×
for lower data rates and converter clocking to reduce the overall
Excellent dynamic performance
system power and ease the filtering requirements. In Mix-Mode™
APPLICATIONS
Broadband communications systems
DOCSIS 3.1 cable modem termination system (CMTS)/
video on demand (VOD)/edge quadrature amplitude
modulation (EQAM)
Wireless communications infrastructure
W-CDMA, LTE, LTE-A, point to point
GENERAL DESCRIPTION
operation, the AD9164 can reconstruct RF carriers in the second
and third Nyquist zones up to 7.5 GHz while still maintaining
exceptional dynamic range. The output current can be programmed
from 8 mA to 38.76 mA. The AD9164 data interface consists of
up to eight JESD204B serializer/deserializer (SERDES) lanes
that are programmable in terms of lane speed and number of
lanes to enable application flexibility.
An SPI interface configures the AD9164 and monitors the status of
all registers. The AD9164 is offered in an 165-ball, 8 mm × 8 mm,
The AD91641 is a high performance, 16-bit digital-to-analog
0.5 mm pitch CSP_BGA package, and an 169-ball, 11 mm × 11 mm,
converter (DAC) and direct digital synthesizer (DDS) that
0.8 mm pitch, CSP_BGA package, including a leaded ball option.
supports update rates to 6 GSPS. The DAC core is based on a
quad-switch architecture coupled with a 2× interpolator filter
that enables an effective DAC update rate of up to 12 GSPS in
some modes. The high dynamic range and bandwidth makes
these DACs ideally suited for the most demanding high speed
radio frequency (RF) DAC applications.
The DDS consists of a bank of 32, 32-bit numerically controlled
oscillators (NCOs), each with its own phase accumulator. When
combined with a 100 MHz serial peripheral interface (SPI) and
PRODUCT HIGHLIGHTS
1. High dynamic range and signal reconstruction bandwidth
supports RF signal synthesis of up to 7.5 GHz.
2. Up to eight lanes JESD204B SERDES interface flexible in
terms of number of lanes and lane speed.
3. Bandwidth and dynamic range to meet DOCSIS 3.1
compliance and multiband wireless communications
standards with margin.
FUNCTIONAL BLOCK DIAGRAM
RESET IRQ
ISET VREF
SDIO
SDO
CS
SCLK
SERDIN0±
SERDIN7±
SYNCOUT±
SYSREF±
SPI
JESD
HB
2×
HB
3×
AD9164
HB
2×
NCO
VREF
NRZ RZ MIX
INV
SINC
DAC
CORE
OUTPUT±
HB
TO JESD
CLOCK
2×,
TO DATAPATH
DISTRIBUTION
4×,
8×
TX_ENABLE
Figure 1.
CLK±
1 Protected by U.S. Patents 6,842,132 and 7,796,971.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9164
Data Sheet
DAC INPUT CLOCK OVERCLOCKING SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Maximum guaranteed speed using the temperature and voltage conditions as shown in Table 2, where VDDx is VDD12_CLK, DVDD,
VDD_1P2, DVDD_1P2, and PLL_LDO_VDD12. Any DAC clock speed over 5.1 GSPS requires a maximum junction temperature that does not
exceed 105°C to avoid damage to the device. See Table 10 for details on maximum junction temperature permitted for certain clock
speeds.
Table 2.
Parameter1
MAXIMUM DAC UPDATE RATE
VDDx = 1.2 V ± 5%
VDDx = 1.2 V ± 2%
VDDx = 1.3 V ± 2%
Test Conditions/Comments
TJMAX = 25°C
TJMAX = 85°C
TJMAX = 105°C
TJMAX = 25°C
TJMAX = 85°C
TJMAX = 105°C
TJMAX = 25°C
TJMAX = 85°C
TJMAX = 105°C
Min Typ Max Unit
6.0 GSPS
5.6 GSPS
5.4 GSPS
6.1 GSPS
5.8 GSPS
5.6 GSPS
6.4 GSPS
6.2 GSPS
6.0 GSPS
1 TJMAX is the maximum junction temperature.
POWER SUPPLY DC SPECIFICATIONS
IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. FIR85 is the finite impulse response with 85 dB digital attenuation.
Table 3.
Parameter
8 LANES, 2× INTERPOLATION (80%), 3 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V
IOVDD1 = 2.5 V
SERDES Supply Currents
VDD_1P2 = 1.2 V
DVDD_1P2 = 1.2 V
PLL_LDO_VDD12 = 1.2 V
SYNC_VDD_3P3 = 3.3 V
8 LANES, 6× INTERPOLATION (80%), 3 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V
IOVDD1 = 2.5 V
Test Conditions/Comments
NCO on, FIR85 on
Includes VDD12_DCD/DLL
Includes VTT_1P2, BIAS_VDD_1P2
Connected to PLL_CLK_VDD12
NCO on, FIR85 on
Includes VDD12_DCD/DLL
Min Typ Max
−119
93.8
3.7
229
−112
621.3
2.5
425.5
62
84.4
9.3
100
150
279
971
2.7
550
86
106
11
93.8
3.7
228.7
−120.7
598.4
2.5
Unit
mA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
mA
mA
mA
mA
Rev. 0 | Page 4 of 134
5 Page 
AD9164
ABSOLUTE MAXIMUM RATINGS
Table 10.
Parameter
ISET, VREF to VBG_NEG
SERDINx±, VTT_1P2,
SYNCOUT±
OUTPUT± to VNEG_N1P2
SYSREF±
CLK± to Ground
RESET, IRQ, CS, SCLK, SDIO,
SDO to Ground
Junction Temperature1
fDAC = 6 GSPS
fDAC ≤ 5.1 GSPS
Ambient Operating
Temperature Range (TA)
Storage Temperature Range
Rating
−0.3 V to VDD25_DAC + 0.3 V
−0.3 V to SYNC_VDD_3P3 + 0.3 V
−0.3 V to VDD25_DAC + 0.3 V
GND − 0.5 V to +2.5 V
−0.3 V to VDD12_CLK + 0.3 V
−0.3 V to IOVDD + 0.3 V
105°C
110°C
−40°C to +85°C
−65°C to +150°C
1 Some operating modes of the device may cause the device to approach or
exceed the maximum junction temperature during operation at supported
ambient temperatures. Removal of heat from the device may require
additional measures such as active airflow, heat sinks, or other measures.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
REFLOW PROFILE
The AD9164 reflow profile is in accordance with the JEDEC
JESD204B criteria for Pb-free devices. The maximum reflow
temperature is 260°C.
THERMAL MANAGEMENT
The AD9164 is a high power device that can dissipate nearly
3 W depending on the user application and configuration.
Because of the power dissipation, the AD9164 uses an exposed
die package to give the customer the most effective method of
controlling the die temperature. The exposed die allows cooling
of the die directly.
Data Sheet
Figure 3 shows the profile view of the device mounted to a user
printed circuit board (PCB) and a heat sink (typically the
aluminum case) to keep the junction (exposed die) below the
maximum junction temperature in Table 10.
CUSTOMER CASE (HEAT SINK)
CUSTOMER THERMAL FILLER
SILICON (DIE)
PACKAGE SUBSTRATE
IC PROFILE
CUSTOMER PCB
Figure 3. Typical Thermal Management Solution
THERMAL RESISTANCE
Typical θJA and θJC values are specified for a 4-layer JEDEC 2S2P
high effective thermal conductivity test board for balled
surface-mount packages. θJA is obtained in still air conditions
(JESD51-2). Airflow increases heat dissipation, effectively reducing
θJA. θJC is obtained with the test case temperature monitored at
the bottom of the package.
ΨJT is thermal characteristic parameters obtained with θJA in still
air test conditions but are not applicable to the CSP_BGA package.
Estimate the junction temperature (TJ) using the following
equations:
TJ = TT + (ΨJT × PDISS)
where:
TT is the temperature measured at the top of the package.
PDISS is the total device power dissipation.
Table 11. Thermal Resistance
Package Type
165-Ball CSP_BGA
169-Ball CSP_BGA
θJA
15.4
14.6
θJC Unit
0.04 °C/W
0.02 °C/W
ESD CAUTION
Rev. 0 | Page 10 of 134
11 Page | ||
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| PDF Descargar | [ Datasheet AD9164.PDF ] | |
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