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PDF AD9261 Data sheet ( Hoja de datos )
| Número de pieza | AD9261 | |
| Descripción | 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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16-Bit, 10 MHz Bandwidth, 30 MSPS to
160 MSPS Continuous Time Sigma-Delta ADC
AD9261
FEATURES
SNR: 83 dB (85 dBFS) to 10 MHz input
SFDR: 87 dBc to 10 MHz input
Noise figure: 15 dB
Input impedance: 1 kΩ
Power: 340 mW
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Selectable bandwidth
2.5 MHz/5 MHz/10 MHz
Output data rate: 30 MSPS to 160 MSPS
Integrated decimation filters
Integrated sample rate converter
On-chip PLL clock multiplier
On-chip voltage reference
Offset binary, Gray code, or twos complement data format
Serial control interface (SPI)
APPLICATIONS
Data acquisition
Automated test equipment
Instrumentation
Medical imaging
GENERAL DESCRIPTION
The AD9261 is a single 16-bit analog-to-digital converter
(ADC) based on a continuous time (CT) sigma-delta (Σ-Δ)
architecture that achieves 87 dBc of dynamic range over a 10 MHz
input bandwidth. The integrated features and characteristics
unique to the continuous time Σ-Δ architecture significantly
simplify its use and minimize the need for external components.
The AD9261 has a resistive input impedance that relaxes the
requirements of the driver amplifier. In addition, a 32× oversam-
pled fifth-order continuous time loop filter significantly attenuates
out-of-band signals and aliases, reducing the need for external
filters at the input.
An external clock input or the integrated integer-N PLL provides
the 640 MHz internal clock needed for the oversampled conti-
nuous time Σ-Δ modulator. On-chip decimation filters and sample
rate converters reduce the modulator data rate from 640 MSPS to a
user-defined output data rate from 30 MSPS to 160 MSPS,
enabling a more efficient and direct interface.
VIN+
VIN–
VREF
CFILT
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
Σ -Δ
MODULATOR
LOW-PASS
DECIMATION
FILTER
SAMPLE
RATE
CONVERTER
CMOS
BUFFER
AD9261
PHASE
LOCKED
LOOP
SERIAL
INTERFACE
OR
D15
D0
PLL_
LOCKED
CLK+
CLK–
DCO
AGND
SDIO SCLK CSB DGND
Figure 1.
The digital output data is presented in offset binary, Gray code,
or twos complement format. A data clock output (DCO) is
provided to ensure proper timing with the receiving logic.
The AD9261 operates on a 1.8 V analog supply and a 1.8 V
to 3.3 V digital supply, consuming 340 mW. The AD9261 is
available in a 48-lead LFCSP and is specified over the industrial
temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. Continuous time Σ-Δ architecture efficiently achieves high
dynamic range and wide bandwidth.
2. Passive input structure reduces or eliminates the require-
ments for a driver amplifier.
3. An oversampling ratio of 32× and high order loop filter
provide excellent alias rejection reducing or eliminating the
need for antialiasing filters.
4. An integrated decimation filter, sample rate converter, PLL
clock multiplier, and voltage reference provide ease of use.
5. This part operates from a single 1.8 V analog power supply
and 1.8 V to 3.3 V output supply.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
AD9261
AC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS,
unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
fIN = 4.2 MHz
fIN = 8.4 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 4.2 MHz
fIN = 8.4 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 4.2 MHz
fIN = 8.4 MHz
NOISE SPECTRAL DENSITY (NSD)
AIN= −2 dBFS
AIN = −40 dBFS
NOISE FIGURE2
TWO-TONE SFDR
fIN1 = 2.1 MHz at −8 dBFS, fIN2 = 2.4 MHz at −8 dBFS
fIN1 = 3.6 MHz at −8 dBFS, fIN2 = 4.2 MHz at −8 dBFS
fIN1 = 7.2 MHz at −8 dBFS, fIN2 = 8.4 MHz at −8 dBFS
ANALOG INPUT BANDWIDTH
APERTURE JITTER
Temp
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
Min Typ
81 83
83
83
13.5
13.5
13.5
87
87
<120
−155
−156
15
93
92.5
92.5
Max Unit
dB
dB
dB
Bits
Bits
Bits
80 dBc
dBc
dBc
−153
−154.5
dB/Hz
dB/Hz
dB
dBc
dBc
dBc
10 MHz
1 ps rms
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Noise figure with respect to 50 Ω. AD9261 internal impedance is 1000 Ω differential. See the AN-835 Application Note for a definition.
DIGITAL DECIMATION FILTERING CHARACTERISTICS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, unless otherwise noted.
Table 3.
Parameter1
Pass-Band Transition
Pass-Band Ripple
Stop Band
Stop Band Attenuation
2.5 MHz BW
Min Typ
2.5
<0.1
3.75 MHz − fS/2
>85
5 MHZ BW
Max Min Typ
3.75 5
<0.1
6.5 MHz − fS/2
>85
10 MHz BW
Max Min Typ
6.5 10
<0.1
13 MHz − fS/2
>85
Max Unit
13 MHz
dB
MHz
dB
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Rev. 0 | Page 4 of 28
5 Page 
AD9261
All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS,
10 MHz bandwidth, output data rate 40 MSPS, TA = 25°C, unless otherwise noted.
00
BANDWIDTH: 10MHz
BANDWIDTH: 10MHz
–20
DATA RATE: 40MSPS
–20
DATA RATE: 40MSPS
fIN: 2.4MHz AT –2dBFS
fIN1: 2.1MHz AT –8dBFS
SNR: 83.2dB
–40 SFDR: 92.6dBc
fIN2: 2.4MHz AT –8dBFS
–40 SFDR: 91.2dBc
–60 –60
–80 –80
–100
–100
–120
–120
–140
–140
–160
0
2 4 6 8 10 12 14 16
FREQUENCY (MHz)
Figure 8. Single-Tone FFT with fIN = 2.4 MHz
18
20
–160
0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (MHz)
Figure 11. Two-Tone FFT with fIN1 = 2.1 MHz and fIN2 = 2.4 MHz
00
BANDWIDTH: 10MHz
BANDWIDTH: 10MHz
–20
DATA RATE: 40MSPS
–20
DATA RATE: 40MSPS
fIN: 4.2MHz AT –2dBFS
fIN1: 3.6MHz AT –8dBFS
SNR: 83.1dB
fIN2: 4.2MHz AT –8dBFS
–40 SFDR: 91.5dBc
–40 SFDR: 92.2dBc
–60 –60
–80 –80
–100
–100
–120
–120
–140
–140
–160
0
0
–20
–40
–60
2 4 6 8 10 12 14 16
FREQUENCY (MHz)
Figure 9. Single-Tone FFT with fIN = 4.2 MHz
18
20
BANDWIDTH: 10MHz
DATA RATE: 40MSPS
fIN: 8.4MHz AT –2dBFS
SNR: 83dB
SFDR: 105.7dBc
–160
0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (MHz)
Figure 12. Two-Tone FFT with fIN1 = 3.6 MHz and fIN2 = 4.2 MHz
0
BANDWIDTH: 10MHz
–20 DATA RATE: 40MSPS
fIN1: 7.2MHz AT –8dBFS
fIN2: 8.4MHz AT –8dBFS
–40 SFDR: 93dBc
–60
–80 –80
–100
–100
–120
–120
–140
–140
–160
0
2 4 6 8 10 12 14 16 18
FREQUENCY (MHz)
Figure 10. Single-Tone FFT with fIN = 8.4 MHz
20
–160
0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (MHz)
Figure 13. Two-Tone FFT with fIN1 = 7.2 MHz and fIN2 = 8.4 MHz
Rev. 0 | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AD9261.PDF ] | |
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