DataSheetWiki


CD4043BMS fiches techniques PDF

Intersil Corporation - CMOS Quad Clocked D Latch

Numéro de référence CD4043BMS
Description CMOS Quad Clocked D Latch
Fabricant Intersil Corporation 
Logo Intersil Corporation 





1 Page

No Preview Available !





CD4043BMS fiche technique
CD4043BMS
CD4044BMS
December 1992
CMOS Quad 3 State R/S Latches
Features
Pinout
• High Voltage Types (20V Rating)
• Quad NOR R/S Latch- CD4043BMS
• Quad NAND R/S Latch - CD4044BMS
• 3 State Outputs with Common Output ENABLE
• Separate SET and RESET Inputs for Each Latch
• NOR and NAND Configuration
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µa at 18V Over Full Pack-
age-Temperature Range;
- 100nA at 18V and 25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of ‘B’
Series CMOS Devices”
Applications
• Holding Register in Multi-Register System
• Four Bits of Independent Storage with Output ENABLE
• Strobed Register
• General Digital Logic
• CD4043BMS for Positive Logic Systems
• CD4044BMS for Negative Logic Systems
Description
CD4043BMS types are quad cross-coupled 3-state CMOS NOR
latches and the CD4044BMS types are quad cross-coupled 3-
state CMOS NAND latches. Each latch has a separate Q output
and individual SET and RESET inputs. The Q outputs are con-
trolled by a common ENABLE input. A logic “1” or high on the
ENABLE input connects the latch states to the Q outputs. A logic
“0” or low on the ENABLE input disconnects the latch states from
the Q outputs, results in an open circuit feature allows common
busing of the outputs.
The CD4043BMS and CD4044BMS are supplied in these 16-
lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4043B Only
*H4T †H4T
*H1C †HIE
*H3X †H6W
†CD4044B Only
CD4043BMS
TOP VIEW
Q4 1
Q1 2
R1 3
S1 4
ENABLE 5
S2 6
R2 7
VSS 8
16 VDD
15 R4
14 S4
13 NC
12 S3
11 R3
10 Q3
9 Q2
NC = NO CONNECTION
CD4044BMS
TOP VIEW
Q4 1
NC 2
S1 3
R1 4
ENABLE 5
R2 6
S2 7
VSS 8
16 VDD
15 S4
14 R4
13 Q1
12 R3
11 S3
10 Q3
9 Q2
NC = NO CONNECTION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-876
File Number 3311

PagesPages 10
Télécharger [ CD4043BMS ]


Fiche technique recommandé

No Description détaillée Fabricant
CD4043BM Quad TRI-STATE NOR(NAND) R/S Latches National Semiconductor
National Semiconductor
CD4043BMS CMOS Quad Clocked D Latch Intersil Corporation
Intersil Corporation

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche