CD4048BMS Datasheet PDF - Intersil Corporation
| Part Number | CD4048BMS | |
| Description | CMOS Multifunction Expandable 8 Input Gate | |
| Manufacturers | Intersil Corporation | |
| Logo |  |
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CD4048BMS
December 1992
CMOS Multifunction
Expandable 8 Input Gate
Features
Pinout
• High-Voltage Type (20V Rating)
• Three State Output
• Many Logic Functions Available in One Package
• Standardize, Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
CD4048BMS
TOP VIEW
J (OUTPUT) 1
Kd 2
H3
INPUTS
G4
F5
E6
Kb 7
VSS 8
16 VDD
15 EXPAND
14 A
13 B
12 C
INPUTS
11 D
10 Ka
9 Kc
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Functional Diagram
Applications
• Selection of Up to 8 Logic Functions
• Digital Control of Logic
• General Purpose Gating Logic
- Decoding
- Encoding
Description
CD4048BMS is an 8-input gate having four control inputs. Three
binary control inputs - Ka, Kb, and Kc - provide the implementa-
tion of eight different logic functions. These functions are OR,
NOR, AND, NAND, OR/AND, OR/NAND, AND/OR and AND/
NOR.
A fourth control input, Kd, provides the user with a 3-state output.
When control input Kd is high, the output is either a logic 1 or a
logic 0 depending on the inner states. When control input Kd is
low, the output is an open circuit. This feature enables the user to
connect this device to a common bus line.
In addition to the eight input lines, an EXPAND input is provided
that permits the user to increase the number of inputs into a
CD4048BMS (see Figure 2). For example, two CD4048BMS’s
can be cascaded to provided a 16-input multifunction gate. When
the EXPAND input is not used, it should be connected to VSS.
The CD4048BMS is supplied in these 16 lead outline packages:
INPUTS
A
B
C
D
EXPAND
INPUTS
E
F
G
H
BINARY CONTROL INPUTS
FUNCTION CONTROL
Ka Kb Kc Kd
3 STATE
CONTROL
10 7 9 2
14
13
12
11
15 I J OUTPUT
6
5
4
3 VSS = 8
VDD = 16
Braze Seal DIP H4S
Frit Seal DIP
H1E
Ceramic Flatpack H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-912
File Number 3314
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Specifications CD4048BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - SSI
Output Current (Sink)
Output Current (Source)
IDD
IOL5
IOH5A
±0.1µA
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A, RONDEL10
IDD, IOL5, IOH5A, RONDEL10
IDD, IOL5, IOH5A, RONDEL10
IDD, IOL5, IOH5A, RONDEL10
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 1
Note 1
OPEN
1
GROUND
2 - 15
VDD
16
9V ± -0.5V
50kHz
25kHz
Static Burn-In 2
Note 1
1
8 2 - 7, 9 - 16
Dynamic Burn-
In Note 1
-
8, 15
2, 16
1
9 - 14
3-7
Irradiation
Note 2
1
8 2 - 7, 9 - 16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
7-916
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| Information | Total 11 Pages | |
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