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CD4072BMS fiches techniques PDF

Intersil Corporation - CMOS OR Gate

Numéro de référence CD4072BMS
Description CMOS OR Gate
Fabricant Intersil Corporation 
Logo Intersil Corporation 





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CD4072BMS fiche technique
CD4071BMS, CD4072BMS
CD4075BMS
December 1992
CMOS OR Gate
Features
Pinout
• High-Voltage Types (20V Rating)
• CD4071BMS Quad 2-Input OR Gate
CD4071BMS
TOP VIEW
• CD4072BMS Dual 4-Input OR Gate
• CD4075BMS Triple 3-Input OR Gate
• Medium Speed Operation:
- tPHL, tPLH = 60ns (typ) at 10V
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Standardized Symmetrical Output Characteristics
A1
B2
J=A+B 3
K=C+C 4
C5
D6
VSS 7
14 VDD
13 H
12 G
11 M = G + H
10 L = E + F
9F
8E
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
CD4071BMS, CD4072BMS and CD4075BMS OR gates pro-
vide the system designer with direct implementation of the
positive-logic OR function and supplement the existing fam-
ily of CMOS gates.
CD4072BMS
TOP VIEW
J=A+B+C+D 1
A2
B3
C4
D5
NC 6
VSS 7
14 VDD
13 K = E +F + G + H
12 H
11 G
10 F
9E
8 NC
NC = NO CONNECTION
The CD4071BMS, CD4072BMS and CD4075BMS are supplied
in these 14 lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4071, CD4072
*H4H †H4Q
H1B
H3W
†CD4075 Only
CD4075BMS
TOP VIEW
A1
B2
D3
E4
F5
K=D+E+F 6
VSS 7
14 VDD
13 G
12 H
11 I
10 L = G + H + I
9 J=A+B+C
8C
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-444
File Number 3323

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