|
|
PDF CD4076BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4076BMS | |
| Descripción | CMOS 4 -Bit D-Type Registers | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CD4076BMS (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
|
No Preview Available !
CD4076BMS
December 1992
CMOS 4 -Bit D-Type Registers
Features
Pinout
• High Voltage Type (20V Rating)
• Three State Outputs
• Input Disabled Without Gating the Clock
• Gated Output Control Lines for Enabling or Disabling
the Outputs
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
CD4076BMS types are four-bit registers consisting of D-type
flip-flops that feature three-state outputs. Data Disable inputs
are provided to control the entry of data into the flip-flops.
When both Data Disable inputs are low, data at the D inputs
are loaded into their respective flip-flops on the next positive
transition of the clock input. Output Disable inputs are also
provided. When the Output Disable inputs are both low, the
normal logic states of the four outputs are available to the
load. The outputs are disabled independently of the clock by
a high logic level at either Output Disable input, and present
a high impedance.
The CD4076BMS is supplied in these 16 lead outline pack-
ages:
CD4076BMS
TOP VIEW
OUTPUT
DISABLE
M1
N2
Q1 3
Q2 4
Q3 5
Q4 6
CLOCK 7
VSS 8
16 VDD
15 RESET
14 DATA 1
13 DATA 2
12 DATA 3
11 DATA 4
10 G2 DATA
INPUT
9 G1 DISABLE
Functional Diagram
DATA INPUT
DISABLE
G1 G2
9 10
14
D1
13
D2
12
D3
11
D4
CLOCK
7
4D - TYPE
FLIP-FLOPS
WITH
AND-OR
LOGIC
15
RESET
OUTPUT
DISABLE
MN
12
3
Q1
4
Q2
5
Q3
6
Q4
VSS = 8
VDD = 16
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1E
H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1029
File Number 3325
1 page  
Specifications CD4076BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES TEMPERATURE MIN MAX UNITS
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
5. If more than one unit is cascaded, TRCL should be made less than or equal to the sum of the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
Propagation Delay Time
SYMBOL
CONDITIONS
IDD VDD = 20V, VIN = VDD or GND
VNTH VDD = 10V, ISS = -10µA
∆VTN VDD = 10V, ISS = -10µA
VTP
∆VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
F
TPHL
TPLH
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
NOTES: 1. All voltages referenced to device GND.
NOTES
1, 4
1, 4
1, 4
TEMPERATURE
+25oC
+25oC
+25oC
MIN
-
-2.8
-
1, 4
+25oC
0.2
1, 4
+25oC
-
1
1, 2, 3, 4
+25oC
+25oC
VOH >
VDD/2
-
3. See Table 2 for +25oC limit.
MAX
25
-0.2
±1
2.8
±1
VOL <
VDD/2
1.35 x
+25oC
Limit
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
UNITS
µA
V
V
V
V
V
ns
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
IOL5
IOH5A
DELTA LIMIT
± 1.0µA
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
7-1033
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CD4076BMS.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CD4076BMS | CMOS 4 -Bit D-Type Registers | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |