PDF CD4094BMS Data sheet ( Hoja de datos )

Número de pieza	CD4094BMS
Descripción	CMOS 8-Stage Shift-and-Store Bus Register
Fabricantes	Intersil Corporation
Logotipo
Hay una vista previa y un enlace de descarga de CD4094BMS (archivo pdf) en la parte inferior de esta página. Total 11 Páginas
No Preview Available ! CD4094BMS December 1992 CMOS 8-Stage Shift-and-Store Bus Register Features Pinout • High Voltage Type (20V Rating) • 3-State Parallel Outputs for Connection to Common Bus • Separate Serial Outputs Synchronous to Both Positive and Negative Clock Edges for Cascading • Medium Speed Operation - 5MHz at 10V (typ) • Standardized Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Speciﬁcations for Description of ‘B’ Series CMOS Devices” CD4094BMS TOP VIEW STROBE 1 DATA 2 CLOCK 3 Q1 4 Q2 5 Q3 6 Q4 7 VSS 8 16 VDD 15 OUTPUT ENABLE 14 Q5 13 Q6 12 Q7 11 Q8 10 Q’S 9 QS Functional Diagram Applications • Serial-to-Parallel Data Conversion • Remote Control Holding Register • Dual-Rank Shift, Hold, and Bus Applications SERIAL OUTPUTS DATA 2 10 Q’S 8-STAGE CLOCK 3 SHIFT 9 QS REGISTER Description CD4094BMS is a 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the STROBE input is high. Data in the storage register appears at the outputs when- ever the OUTPUT-ENABLE signal is high. Two serial outputs are available for cascading a number of CD4094BMS devices. Data is available at the QS serial output terminal on positive clock edges to allow for high-speed opera- tion in cascaded systems in which the clock rise time is fast. The same serial information, available at the Q’S terminal on the next negative clock edge, provides a means for cascading CD4094BMS devices when the clock rise time is slow. The CD4094BMS is supplied in these 16 lead outline packages: STROBE 1 8-BIT STORAGE REGISTER OUTPUT ENABLE 15 3-STATE OUTPUTS VDD = 16 VSS = 8 PARALLEL OUTPUTS Q1 - Q8 (TERMINALS 4, 5, 6, 7, 14, 13, 12, 11, RESPECTIVELY) Braze Seal DIP H4X Frit Seal DIP H1F Ceramic Flatpack H6W CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 \| Copyright © Intersil Corporation 1999 7-1083 File Number 3194 1 page Speciﬁcations CD4094BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Minimum Strobe Pulse Width Input Capacitance SYMBOL CONDITIONS TW VDD = 5V VDD = 10V VDD = 15V CIN Any Input NOTES 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC +25oC +25oC +25oC MIN - - - - MAX 200 80 70 7.5 UNITS ns ns ns pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. 5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional Propagation Delay Time SYMBOL CONDITIONS IDD VDD = 20V, VIN = VDD or GND VNTH VDD = 10V, ISS = -10µA ∆VTN VDD = 10V, ISS = -10µA VTP ∆VTP VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA F TPHL TPLH VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND VDD = 5V NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. NOTES 1, 4 1, 4 1, 4 TEMPERATURE +25oC +25oC +25oC MIN - -2.8 - 1, 4 +25oC 0.2 1, 4 +25oC - 1 1, 2, 3, 4 +25oC +25oC VOH > VDD/2 - 3. See Table 2 for +25oC limit. 4. Read and Record MAX 25 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V ns TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 Output Current (Sink) Output Current (Source) IDD IOL5 IOH5A ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading CONFORMANCE GROUP Initial Test (Pre Burn-In) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS 100% 5004 1, 7, 9 READ AND RECORD IDD, IOL5, IOH5A 7-1087 5 Page CD4094BMS Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: Thickness: 11kÅ − 14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speciﬁcations at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Ofﬁce Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 1093 11 Page

Páginas	Total 11 Páginas
PDF Descargar	[ Datasheet CD4094BMS.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
CD4094BMS	CMOS 8-Stage Shift-and-Store Bus Register	Intersil Corporation

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar