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PDF EM47FM0888MBA Data sheet ( Hoja de datos )
| Número de pieza | EM47FM0888MBA | |
| Descripción | 4Gb Double DATA RATE 3 SDRAM | |
| Fabricantes | Eorex | |
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EM47FM0888MBA
4Gb (64M×8Bank×8) Double DATA RATE 3 low voltage SDRAM
Features
• JEDEC Standard VDD/VDDQ = 1.35V(1.283-1.45V)
• All inputs and outputs are compatible with SSTL_15
interface.
• Fully differential clock inputs (CK, /CK) operation.
• Eight Banks
• Posted CAS by programmable additive latency
• Bust length: 4 with Burst Chop (BC) and 8.
• CAS Write Latency (CWL): 5, 6, 7, 8
• CAS Latency (CL): 6, 7, 8, 9, 10, 11
• Write Latency (WL) =Read Latency (RL) -1.
• Bi-directional Differential Data Strobe (DQS).
• Data inputs on DQS centers when write.
• Data outputs on DQS, /DQS edges when read.
• On chip DLL align DQ, DQS and /DQS transition
with CK transition.
• DM mask write data-in at the both rising and falling
edges of the data strobe.
• Sequential & Interleaved Burst type available both
for 8 & 4 with BC.
• Multi Purpose Register (MPR) for pre-defined
pattern read out
• On Die Termination (ODT) options: Synchronous
ODT, Dynamic ODT, and Asynchronous ODT
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
• Refresh Interval: 7.8us Tcase between 0°C ~ 85°C
• RoHS Compliance
• Driver Strength: RZQ/7, RZQ/6(RZQ=240Ω)
• High Temperature Self-Refresh rate enable
• ZQ calibration for DQ drive and ODT
• RESET pin for initialization and reset function
Description
The EM47FM0888MBA is a high speed Double Date
Rate 3 (DDR3) low voltage Synchronous DRAM
fabricated with ultra high performance CMOS
process containing 4,294,967,296 bits which
organized as 64Mbits x 8 banks by 8 bits. This
synchronous device achieves high speed
double-data-rate transfer rates of up to 1600
Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key
DDR3 SDRAM features: (1) posted CAS with
additive latency, (2) write latency = read latency -1,
(3) On Die Termination, (4) programmable driver
strength data,(5) seamless BL4 access with
bank-grouping. All of the control and address inputs
are synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross
point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional
differential data strobes (DQS and /DQS) in a source
synchronous fashion. The address bus is used to
convey row, column and bank address information in
a /RAS and /CAS multiplexing style. The 4Gb DDR3
devices operates with a single power supply:
1.35V(1.283-1.45V) VDD and VDDQ. Available
package: FBGA-78Ball (with 0.8mm x 0.8mm ball
pitch)
Jul. 2012
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1 page  
EM47FM0888MBA
Pin Description (Continued)
C3,D3
B7,A7
F3, G3, H3
DQS, DQS
TDQS,
TDQS
RAS ,
CAS , WE
(Data Strobe)
Output with read data, input with write data. Edge-aligned with read data,
centered in write data. The data strobe DQS is paired with differential
signal /DQS to provide differential pair signaling to the system during
reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
(Termination Data Strobe)
When enabled via Mode Register A11=1 in MR1, DRAM will enable the
same termination resistance function on TDQS/TDQS that is applied to
DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS
will provide the data mask function and TDQS is not used.
(Command Inputs)
RAS , CAS and WE (along with CS ) define the command being
entered.
B3,C7,C2,C8,E3,
E8,D2,E7
A2,A9,D7,G2,G8,
K1,K9,M1,M9/A1,
A8,B1,D8,F2,F8,J1
,J9,L1,L9,N1,N9
B9,C1,E2,E9
/B2,B8,C9,D1,D9
H8
N2
E1
J8
A3,F1,H1,F9,
H9
DQ0~7
VDD/VSS
VDDQ
/VSSQ
ZQ
RESET
VREFDQ
VREFCA
NC
(Data Input/Output)
Data inputs and outputs are on the same pin.
(Power Supply/Ground)
VDD and VSS are power supply for internal circuits.
(DQ Power Supply/DQ Ground)
VDDQ and VSSQ are power supply for the output buffers.
(ZQ Calibration)
Reference pin for ZQ calibration
(Active Low Asynchronous Reset)
Reset is active when RESET is LOW, and inactive when RESET is
HIGH. RESET must be HIGH during normal operation. RESET is a
CMOS rail to rail signal with DC high and low at 80% and 20% of VDD,
i.e. 1.20V for DC high and 0.30V for DC low.
(Reference Voltage)
Reference voltage for DQ
(Reference Voltage)
Reference voltage for CA
(No Connection)
No internal electrical connection is present.
Note: Input pins only BA0-BA2, A0-A15, RAS , CAS , WE , CS , CKE, ODT and RESET do not supply
termination.
Jul. 2012
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5 Page 
EM47FM0888MBA
AC and DC Output Measurement Levels
Symbol Parameter
Specification Units Note
VOH(DC)
VOM(DC)
VOL(DC)
VOH(AC)
VOL(AC)
VOHdiff(DC)
VOLdiff(DC)
DC output high measurement level (for IV curve linearity)
DC output middle measurement level (for IV curve linearity)
DC output low measurement level (for IV curve linearity)
AC output high measurement level (for output slew rate)
AC output low measurement level (for output slew rate)
AC differential output high measurement level (for output
slew rate)
AC differential output low measurement level (for output
slew rate)
0.8*VDDQ
0.5*VDDQ
0.2*VDDQ
VTT+0.1*VDDQ
VTT-0.1*VDDQ
0.2*VDDQ
-0.2*VDDQ
V
V
V
V
V
V
V
1
1
2
2
Notes1. The swing of ±0.1 × VDDQ is based on approximately 50% of the static single-ended output high or
low swing with a driver impedance of 34Ω and an effective test load of 25Ω to VTT = VDDQ/2 at each of the
differential outputs.
Notes2. The swing of ±0.2 × VDDQ is based on approximately 50% of the static single-ended output high or
low swing with a driver impedance of 34Ω and an effective test load of 25Ω to VTT = VDDQ/2 at each of the
differential outputs.
DQS Output Crossing Voltage - VOX (DDR3-1600 or Higher Speed Bin)
Symbol
Parameters
DQS, /DQS differential slew rate
5V/ns 6V/ns 7V/ns 8V/ns 9V/ns
Deviation of DQS,
VOX (AC) max. /DQS output
+100 +120 +140 +160 +180
cross point
VOX (AC) min.
voltage from
0.5*VDDQ
-100 -120 -140 -160 -180
10V/ns
+200
-200
11V/ns
+200
-200
12V/ns
+200
-200
Unit
mV
mV
DQS Output Crossing Voltage - VOX (DDR3-1333 or Lower Speed Bin)
Symbol
Parameters
DQS, /DQS differential slew rate
5V/ns 6V/ns 7V/ns 8V/ns 9V/ns
Deviation of DQS,
VOX (AC) max. /DQS output
+125 +150 +175 +200 +225
cross point
VOX (AC) min.
voltage from
0.5*VDDQ
-125 -150 -175 -200 -225
10V/ns
+225
-225
11V/ns
+225
-225
12V/ns
+225
-225
Unit
mV
mV
Notes1. Measured using an effective test load of 25Ω to 0.5* VDDQ at each of the differential outputs.
Notes2. For a differential slew rate in between the listed values, the VOX value may be obtained by linear
interpolation.
Notes3. The DQS, /DQS pins under test are not required to be able to drive each of the slew rates listed in the
table; the pins under test will provide one VOX value when tested with specified test condition. The DQS and
/DQS differential slew rate when measuring VOX determines which VOX limits to use.
Jul. 2012
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