PDF EM48AM1644LBB Data sheet ( Hoja de datos )

Número de pieza	EM48AM1644LBB
Descripción	256Mb Synchronous DRAM
Fabricantes	Eorex
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No Preview Available ! eorex Preliminary EM48AM1644LBB 256Mb (4M×4Bank×16) Synchronous DRAM Features • 2 x 4 banks x 2 Mbit x 16 organisation ( Two 128MBit chips stacked in multi-chip package) • Fully Synchronous to Positive Clock Edge • Single 1.8V ±0.1V Power Supply • LVCMOS Compatible with Multiplexed Address • Programmable Burst Length –1/2/4/8/ full Page • Programmable CAS Latency (C/L) - 2 or 3 • Data Mask (DQM) for Read / Write Masking • Programmable Wrap Sequence – Sequential (B/L = 1/2/4/8/full Page) – Interleave (B/L = 4/8) • Burst Read with Single-bit Write Operation • Deep Power Down Mode. • Auto Refresh and Self Refresh • Special Function Support. – PASR (Partial Array Self Refresh) – Auto TCSR (Temperature Compensated Self Refresh) • Programmable Driver Strength Control – Full Strength or 1/2, 1/4 of Full Strength • 4,096 Refresh Cycles / 64ms (15.625us) Description The EM48AM1684LBB is Synchronous Dynamic Random Access Memory (SDRAM) organized as 2 x 4 banks x 2 Mbit by 16 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 256Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 1.8V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVCMOS. Available packages:TFBGA 54B 12mm x 8mm. Ordering Information Part No EM48AM1644LBB-75F EM48AM1644LBB-75FE Organization 2 die X 8M X 16 2 die X 8M X 16 Max. Freq 133MHz @CL3 133MHz @CL3 Package Grade Pb TFBGA -54B Commercial Free TFBGA -54B Extend temp. Free Jul. 2006 * EOREX reserves the right to change products or specification without notice. www.eorex.com 1/19 1 page eorex Preliminary EM48AM1644LBB Recommended DC Operating Conditions (VDD=3.3V±0.3V, TA=0°C ~ 70°C) Symbol Parameter Test Conditions ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4 ICC5 ICC6 Operating Current (Note 1) Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non-power Down Mode Operating Current (Burst Mode) (Note 2) Refresh Current (Note 3) Self Refresh Current Burst length=1, tRC≥tRC(min.), IOL=0mA, One bank active CKE≤VIL(max.), tCK=15ns CKE≤VIL(max.), tCK= ∞ CKE≥VIL(min.), tCK=15ns, /CS≥VIH(min.) Input signals are changed one time during 30ns CKE≥VIL(min.), tCK= ∞ , Input signals are stable CKE≤VIL(max.), tCK=15ns CKE≤VIL(max.), tCK= ∞ CKE≥VIL(min.), tCK=15ns, /CS≥VIH(min.) Input signals are changed one time during 30ns CKE≥VIL(min.), tCK= ∞ , Input signals are stable tCCD≥2CLKs, IOL=0mA tRC≥tRC(min.) CKE≤0.2V ICC7 Deep Power Down Mode Current All voltages referenced to VSS. Note 1: ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 2: ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 3: Input signals are changed only one time during tCK (min.) Note 4: Standard power version. Max. 80 1 1 20 2 10 2 40 20 100 180 0.4 (Note 4) 20 Recommended DC Operating Conditions (Continued) Units mA mA mA mA mA mA mA mA mA mA mA mA uA Symbol Parameter IIL Input Leakage Current IOL Output Leakage Current VOH High Level Output Voltage VOL Low Level Output Voltage Test Conditions 0≤VI≤VDDQ, VDDQ=VDD All other pins not under test=0V 0≤VO≤VDDQ, DOUT is disabled IO=-0.1mA IO=+0.1mA Min. Typ. -1 -1.5 0.9VDD Max. Units +1 uA +1.5 0.2 uA V V Jul. 2006 www.eorex.com 5/19 5 Page eorex Preliminary EM48AM1644LBB Burst Type (A3) Burst Length A2 A1 A0 Sequential Addressing Interleave Addressing XX0 01 2 XX0 10 01 10 X00 0123 0123 X01 1230 4 X10 2301 1032 2301 X11 3012 3210 000 01234567 01234567 001 12345670 10325476 010 23456701 23016745 011 34567012 8 100 45670123 32107654 45670123 101 56701234 54761032 110 67012345 67452301 111 70123456 76543210 Full Page* nnn Cn Cn+1 Cn+2…… * Page length is a function of I/O organization and column addressing ×16 (CA0 ~ CA8): Full page = 512bits - Jul. 2006 11/19 www.eorex.com 11 Page

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