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PDF SST25VF064C Data sheet ( Hoja de datos )
| Número de pieza | SST25VF064C | |
| Descripción | 64 Mbit SPI Serial Dual I/O Flash | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Obsolete Device
Please contact Microchip Sales for replacement information.
64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
EOL Data Sheet
The SST 25 series Serial Flash family features a four-wire, SPI-compatible inter-
face that allows for a low pin-count package which occupies less board space and
ultimately lowers total system costs. SST25VF064C SPI serial flash memory is
manufactured with SST proprietary, high-performance CMOS SuperFlash tech-
nology. The split-gate cell design and thick-oxide tunneling injector attain better
reliability and manufacturability compared with alternate approaches.
Features
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• Dual Input/Output Support
– Fast-Read Dual-Output Instruction
– Fast-Read Dual I/O Instruction
• High Speed Clock Frequency
– 80 MHz for High-Speed Read (0BH)
– 75 MHz for Fast-Read Dual-Output (3BH)
– 50 MHz for Fast-Read Dual I/O (BBH)
– 33 MHz for Read Instruction (03H)
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 12 mA (typical @ 80 MHz) for sin-
gle-bit read)
– Active Read Current: 14 mA (typical @ 75MHz) for dual-
bit read)
– Standby Current: 5 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
• Fast Erase
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
• Page-Program
– 256 Bytes per page
– Single and Dual Input support
– Fast Page-Program time in 1.5 ms (typical)
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
– Write protection through Block-Protection bits in status
register
• Security ID
– One-Time Programmable (OTP) 256 bit, Secure ID
- 64 bit Unique, Factory Pre-Programmed identifier
- 192 bit User-Programmable
• Temperature Range
– Commercial = 0°C to +70°C
– Industrial: -40°C to +85°C
• Packages Available
– 16-lead SOIC (300 mils)
– 8-contact WSON (6mm x 8mm)
– 8-lead SOIC (200 mils)
• All devices are RoHS compliant
©2015 Silicon Storage Technology, Inc.
www.microchip.com
DS20005036C
04/15
1 page  
64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Memory Organization
EOL Data Sheet
The SST25VF064C SuperFlash memory array is organized in uniform 4 KByte erasable sectors with
32 KByte overlay blocks and 64 KByte overlay erasable blocks.
Device Operation
The SST25VF064C is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consists of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25VF064C supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
CE#
MODE 3
SCK MODE 0
MODE 3
MODE 0
SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DON'T CARE
MSB
HIGH IMPEDANCE
SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1392 F04.0
Figure 3: SPI Protocol
Reset/Hold Mode
The RST#/HOLD# pin provides either a hardware reset or a hold pin. From power-on, the RST#/
HOLD# pin defaults as a hardware reset pin (RST#). The Hold mode for this pin is a user selected
option where an EHLD instruction enables the Hold mode. Once selected as a hold pin (HOLD#), the
RST#/HOLD# pin will be configured as a HOLD# pin, and goes back to RST# pin only after a power-off
and power-on sequence.
©2015 Silicon Storage Technology, Inc.
5
DS20005036C
04/15
5 Page 
64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Instructions
EOL Data Sheet
Instructions are used to read, write (Erase and Program), and configure the SST25VF064C. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The Write-
Enable (WREN) instruction must be executed prior any Page-Program, Dual-Input Page-Program,
Sector-Erase, Block-Erase, Write-Status-Register, Chip-Erase, Program SID, or Lockout SID instruc-
tions. The complete list of instructions is provided in Table 6.
All instructions are synchronized off a high to low transition of CE#. Inputs will be accepted on the ris-
ing edge of SCK starting with the most significant bit. CE# must be driven low before an instruction is
entered and must be driven high after the last bit of the instruction has been shifted in (except for
Read, Read-ID, and Read-Status-Register instructions). Any low to high transition on CE#, before
receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the
device to standby mode. Instruction commands (Op Code), addresses, and data are all input from the
most significant bit (MSB) first.
Table 6: Device Operation Instructions
Instruction
Description
Op Code Cycle1
Address
Cycle(s)2
Read
Read Memory
0000 0011b (03H)
3
Fast-Read Dual I/O
Read Memory with Dual Address Input 1011 1011b (BBH)
and Data Output
33
Fast-Read Dual-Out- Read Memory with Dual Output
put
0011 1011b (3BH)
3
High-Speed Read Read Memory at Higher Speed
0000 1011b (0BH)
3
Sector-Erase4
Erase 4 KByte of memory array
0010 0000b (20H)
3
32 KByte Block-Erase5 Erase 32KByte block of memory array 0101 0010b (52H)
3
64 KByte Block-Erase6 Erase 64 KByte block of memory array 1101 1000b (D8H)
3
Chip-Erase
Erase Full Memory Array
0110 0000b (60H) or
1100 0111b (C7H)
0
Page-Program
To Program 1 to 256 Data Bytes
0000 0010b (02H)
3
Dual-Input Page-
Program
To Program 1 to 256 Data Bytes
1010 0010b (A2H)
3
RDSR7
Read-Status-Register
0000 0101b (05H)
0
EWSR
Enable-Write-Status-Register
0101 0000b (50H)
0
WRSR
Write-Status-Register
0000 0001b (01H)
0
WREN
Write-Enable
0000 0110b (06H)
0
WRDI
Write-Disable
0000 0100b (04H)
0
RDID8
Read-ID
1001 0000b (90H) or
1010 1011b (ABH)
3
JEDEC-ID
JEDEC ID Read
1001 1111b (9FH)
0
EHLD
Enable HOLD# pin functionality of the 1010 1010b (AAH)
RST#/HOLD# pin
0
Read SID
Read Security ID
1000 1000b (88H)
1
Program SID9
Program User Security ID area
1010 0101b (A5H)
1
Lockout SID9
Lockout Security ID Programming 1000 0101b (85H)
0
1. One bus cycle is eight clock periods.
Dummy
Cycle(s)
0
13
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Data
Cycle(s)
1 to
1 to 3
1 to 3
1 to
0
0
0
0
1 to 256
1 to 1283
1 to
0
1
0
0
1 to
3 to
0
1 to 32
1 to 24
0
T6.0 25036
©2015 Silicon Storage Technology, Inc.
11
DS20005036C
04/15
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SST25VF064C.PDF ] | |
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