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PDF SST26VF064BA Data sheet ( Hoja de datos )
| Número de pieza | SST26VF064BA | |
| Descripción | 2.5V/3.0V 64 Mbit Serial Quad I/O (SQI) Flash Memory | |
| Fabricantes | Microchip | |
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SST26VF064B / SST26VF064BA
2.5V/3.0V 64 Mbit Serial Quad I/O (SQI) Flash Memory
Features
• Single Voltage Read and Write Operations
- 2.7-3.6V or 2.3-3.6V
• Serial Interface Architecture
- Nibble-wide multiplexed I/O’s with SPI-like serial
command structure
- Mode 0 and Mode 3
- x1/x2/x4 Serial Peripheral Interface (SPI) Protocol
• High Speed Clock Frequency
- 2.7-3.6V: 104 MHz max
- 2.3-3.6V: 80 MHz max
• Burst Modes
- Continuous linear burst
- 8/16/32/64 Byte linear burst with wrap-around
• Superior Reliability
- Endurance: 100,000 Cycles (min)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Read current: 15 mA (typical @ 104 MHz)
- Standby Current: 15 µA (typical)
• Fast Erase Time
- Sector/Block Erase: 18 ms (typ), 25ms (max)
- Chip Erase: 35 ms (typ), 50 ms (max)
• Page-Program
- 256 Bytes per page in x1 or x4 mode
• End-of-Write Detection
- Software polling the BUSY bit in status register
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Four 8 KByte top and bottom parameter
overlay blocks
- One 32 KByte top and bottom overlay block
- Uniform 64 KByte overlay blocks
• Write-Suspend
- Suspend Program or Erase operation to access
another block/sector
• Software Reset (RST) mode
• Software Protection
- Individual-Block Write Protection with permanent
lock-down capability
- 64 KByte blocks, two 32 KByte blocks, and
eight 8 KByte parameter blocks
- Read Protection on top and bottom 8 KByte
parameter blocks
• Security ID
- One-Time Programmable (OTP) 2 KByte, Secure ID
- 64 bit unique, factory pre-programmed identifier
- User-programmable area
• Temperature Range
- Industrial: -40°C to +85°C
- Extended: -40°C to +105°C
• Packages Available
- 8-contact WDFN (6mm x 5mm)
- 8-contact WDFN (6mm x 8 mm)
- 8-lead SOIJ (5.28 mm)
- 16-lead SOIC (7.50 mm)
- 24-ball TBGA (6mm x 8mm)
• All devices are RoHS compliant
Product Description
The Serial Quad I/O™ (SQI™) family of flash-memory
devices features a six-wire, 4-bit I/O interface that
allows for low-power, high-performance operation in a
low pin-count package. SST26VF064B/064BA also
support full command-set compatibility to traditional
Serial Peripheral Interface (SPI) protocol. System
designs using SQI flash devices occupy less board
space and ultimately lower system costs.
All members of the 26 Series, SQI family are manufac-
tured with proprietary, high-performance CMOS Super-
Flash® technology. The split-gate cell design and thick-
oxide tunneling injector attain better reliability and man-
ufacturability compared with alternate approaches.
SST26VF064B/064BA significantly improve perfor-
mance and reliability, while lowering power consump-
tion. These devices write (Program or Erase) with a
single power supply of 2.3-3.6V. The total energy con-
sumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range,
the SuperFlash technology uses less current to pro-
gram and has a shorter erase time, the total energy
consumed during any Erase or Program operation is
less than alternative flash memory technologies.
SST26VF064B/064BA are offered in 8-contact WDFN
(6 mm x 5 mm or 6mm x 8mm), 8-lead SOIJ (5.28 mm),
16-lead SOIC (7.50 mm), and 24-ball TBGA. See Fig-
ure 2-2 for pin assignments.
Two configurations are available upon order.
SST26VF064B default at power-up has the WP# and
HOLD# pins enabled, and the SIO2 and SIO3 pins dis-
abled, to initiate SPI-protocol operations.
2015 Microchip Technology Inc.
DS20005119G-page 1
1 page  
SST26VF064B / SST26VF064BA
FIGURE 2-4:
PIN DESCRIPTION FOR 24-BALL TBGA
Top View
4
NC
VDD
WP#/ HOLD#/ NC
SIO2 SIO3
NC
3
NC VSS
NC SI/ NC
SIO0
NC
2
NC SCK CE# S0/ NC NC
SIO1
1
NC NC NC NC NC NC
A B C D E F T4D-P1.0
TABLE 2-1:
Symbol
SCK
SIO[3:0]
SI
SO
CE#
WP#
HOLD#
VDD
VSS
PIN DESCRIPTION
Pin Name
Functions
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
Serial Data
Input/Output
To transfer commands, addresses, or data serially into the device or data out of
the device. Inputs are latched on the rising edge of the serial clock. Data is
shifted out on the falling edge of the serial clock. The Enable Quad I/O (EQIO)
command instruction configures these pins for Quad I/O mode.
Serial Data Input
for SPI mode
To transfer commands, addresses or data serially into the device. Inputs are
latched on the rising edge of the serial clock. SI is the default state after a power
on reset.
Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge
for SPI mode
of the serial clock. SO is the default state after a power on reset.
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence; or in the case of Write operations,
for the command/data input sequence.
Write Protect
The WP# is used in conjunction with the WPEN and IOC bits in the Configura-
tion register to prohibit write operations to the Block-Protection register. This pin
only works in SPI, single-bit and dual-bit Read mode.
Hold
Temporarily stops serial communication with the SPI Flash memory while the
device is selected. This pin only works in SPI, single-bit and dual-bit Read mode
and must be tied high when not in use.
Power Supply
To provide power supply voltage.
Ground
2015 Microchip Technology Inc.
DS20005119G-page 5
5 Page 
SST26VF064B / SST26VF064BA
4.5.1 WRITE-ENABLE LATCH (WEL)
The Write-Enable Latch (WEL) bit indicates the status
of the internal memory’s Write-Enable Latch. If the
WEL bit is set to ‘1’, the device is write enabled. If the
bit is set to ‘0’ (reset), the device is not write enabled
and does not accept any memory Program or Erase,
Protection Register Write, or Lock-Down commands.
The Write-Enable Latch bit is automatically reset under
the following conditions:
• Power-up
• Reset
• Write-Disable (WRDI) instruction
• Page-Program instruction completion
• Sector-Erase instruction completion
• Block-Erase instruction completion
• Chip-Erase instruction completion
• Write-Block-Protection register instruction
• Lock-Down Block-Protection register instruction
• Program Security ID instruction completion
• Lockout Security ID instruction completion
• Write-Suspend instruction
• SPI Quad Page program instruction completion
• Write Status Register
4.5.2
WRITE SUSPEND ERASE STATUS
(WSE)
The Write Suspend-Erase status (WSE) indicates
when an Erase operation has been suspended. The
WSE bit is ‘1’ after the host issues a suspend command
during an Erase operation. Once the suspended Erase
resumes, the WSE bit is reset to ‘0’.
4.5.3
WRITE SUSPEND PROGRAM
STATUS (WSP)
The Write Suspend-Program status (WSP) bit indicates
when a Program operation has been suspended. The
WSP is ‘1’ after the host issues a suspend command
during the Program operation. Once the suspended
Program resumes, the WSP bit is reset to ‘0’.
4.5.4
WRITE PROTECTION LOCK-DOWN
STATUS (WPLD)
The Write Protection Lock-Down status (WPLD) bit
indicates when the Block-Protection register is locked-
down to prevent changes to the protection settings.
The WPLD is ‘1’ after the host issues a Lock-Down
Block-Protection command. After a power cycle, the
WPLD bit is reset to ‘0’.
4.5.5 SECURITY ID STATUS (SEC)
The Security ID Status (SEC) bit indicates when the
Security ID space is locked to prevent a Write com-
mand. The SEC is ‘1’ after the host issues a Lockout
SID command. Once the host issues a Lockout SID
command, the SEC bit can never be reset to ‘0.’
4.5.6 BUSY
The Busy bit determines whether there is an internal
Erase or Program operation in progress. If the BUSY
bit is ‘1’, the device is busy with an internal Erase or
Program operation. If the bit is ‘0’, no Erase or Program
operation is in progress.
4.5.7 CONFIGURATION REGISTER
The Configuration register is a Read/Write register that
stores a variety of configuration information. See Table
4-3 for the function of each bit in the register.
TABLE 4-3: CONFIGURATION REGISTER
Bit Name
Function
Default at Power-up
0 RES
IOC
1
Reserved
I/O Configuration for SPI Mode
1 = WP# and HOLD# pins disabled
0 = WP# and HOLD# pins enabled
0
01
2 RES
BPNV
3
Reserved
Block-Protection Volatility State
1 = No memory block has been permanently locked
0 = Any block has been permanently locked
0
1
4 RES
Reserved
0
5 RES
Reserved
0
6 RES
Reserved
WPEN Write-Protection Pin (WP#) Enable
7 1 = WP# enabled
0 = WP# disabled
0
02
Read/Write (R/W)
R
R/W
R
R
R
R
R
R/W
1. SST26VF064B default at Power-up is ‘0’
SST26VF064BA default at Power-up is ‘1’
2. Factory default setting. This is a non-volatile bit; default at power-up will be the setting prior to power-down.
2015 Microchip Technology Inc.
DS20005119G-page 11
11 Page | ||
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| PDF Descargar | [ Datasheet SST26VF064BA.PDF ] | |
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