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PDF SST38VF6404 Data sheet ( Hoja de datos )
| Número de pieza | SST38VF6404 | |
| Descripción | 64 Mbit (x16) Advanced Multi-Purpose Flash Plus | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SST38VF6404 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Not recommended for new designs.
Please use SST38VF6401B/6402B/6403B/64040B
64 Mbit (x16) Advanced Multi-Purpose Flash Plus
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
Not Recommended for New Designs
The SST38VF6401/6402/6403/6404 are 4M x16 CMOS Advanced Multi-Purpose
Flash Plus (Advanced MPF+) devices manufactured with proprietary, high-perfor-
mance CMOS Super- Flash technology. The split-gate cell design and thick-oxide
tunneling injector attain better reliability and manufacturability compared with
alternate approaches. The SST38VF6401/6402/6403/6404 write (Program or
Erase) with a 2.7-3.6V power supply. This device conforms to JEDEC standard
pin assignments for x16 memories.
Features
• Organized as 4M x16
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Superior Reliability
– Endurance: 100,000 Cycles minimum
– Greater than 100 years Data Retention3
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 4 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• 128-bit Unique ID
• Security-ID Feature
– 256 Word, user One-Time-Programmable
• Protection and Security Features
– Hardware Boot Block Protection/WP# Input Pin, Uni-
form (32 KWord) and Non-Uniform (8 KWord) options
available
– User-controlled individual block (32 KWord) protection,
using software only methods
– Password protection
• Hardware Reset Pin (RST#)
• Fast Read and Page Read Access Times:
– 90 ns Read access time
– 25 ns Page Read access times
- 4-Word Page Read buffer
• Latched Address and Data
• Fast Erase Times:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
• Erase-Suspend/-Resume Capabilities
• Fast Word and Write-Buffer Programming Times:
– Word-Program Time: 7 µs (typical)
– Write Buffer Programming Time: 1.75 µs / Word (typical)
- 16-Word Write Buffer
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
– RY/BY# Output
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• CFI Compliant
• Packages Available
– 48-lead TSOP
– 48-ball TFBGA
• All devices are RoHS compliant
© 2015
www.microchip.com
DS-20005015B
08/15
1 page  
64 Mbit (x16) Advanced Multi-Purpose Flash Plus
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
Not Recommended for New Designs
Table 1: Pin Description
Symbol Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses.
During Sector-Erase AMS-A12 address lines will select the sector.
During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP#
Write Protect
To protect the top/bottom boot block from Erase/Program operation when
grounded.
RY/BY# Ready/Busy
To indicate when the device is actively programming or erasing.
RST#
Reset
To reset and return the device to Read mode.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
VDD Power Supply To provide power supply voltage: 2.7-3.6V
VSS Ground
NC No Connection Unconnected pins.
1. AMS = Most significant address
AMS = A21 for SST38VF6401/6402/6403/6404
T1.0 20005015
© 2015
DS-20005015B
08/15
5
5 Page 
64 Mbit (x16) Advanced Multi-Purpose Flash Plus
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
Not Recommended for New Designs
If the Write-to-Buffer or Program Buffer-to-Flash operation aborts, then DQ1 = 1 and the device enters
Write-Buffer-Abort mode. To execute another operation, a Write-to-Buffer Abort-Reset command must
be issued to clear DQ1 and return the device to standard read mode.
After the Write-to-Buffer and Program Buffer-to-Flash commands are successfully issued, the pro-
gramming operation can be monitored using Data# Polling, Toggle Bits, and RY/BY#.
Sector/Block-Erase Operations
The Sector-Erase and Block-Erase operations allow the system to erase the device on a sector-by-
sector, or block-by-block, basis. The SST38VF6401/6402/6403/6404 offer both Sector-Erase and Block-
Erase modes.
The Sector-Erase architecture is based on a sector size of 4 KWords. The Sector-Erase command can
erase any 4 KWord sector (S0 - S1023).
The Block-Erase architecture is based on block size of 32 KWords. In SST38VF6401 and
SST38VF6402 devices, the Block-Erase command can erase any 32KWord Block (B0-B127). For the
non-uniform boot block devices, SST38VF6403 and SST38VF6404, the Block-Erase command can
erase any 32 KWord block except the block that contains the boot area. In the boot area, Block-Erase
behaves like Sector-Erase, and only erases a 4KWord sector. For the SST38VF6403 device, a Block-
Erase executed on the Boot Block (B0), will result in the device erasing a 4KWord sector in B0 located
at A21-A12. For the SST38VF6404 device, a Block-Erase executed on the Boot Block (B127), will result
in the device erasing a 4KWord sector in B127 located at A21-A12.
The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase
command (50H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated
by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA)
in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse,
while the command (50H or 30H) is latched on the rising edge of the sixth WE# pulse. The internal
Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined
using either Data# Polling or Toggle Bit methods. The RY/BY# pin can also be used to monitor the
erase operation. For more information, see Figures 14 and 15 for timing waveforms and Figure 29 for
the flowchart.
Any commands, other than Erase-Suspend, issued during the Sector- or Block-Erase operation are
ignored. Any attempt to Sector- or Block-Erase memory inside a block protected by Volatile Block Pro-
tection, Non-Volatile Block Protection, or WP# (low) will be ignored. During the command sequence,
WP# should be statically held high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing
data to be read or programmed into any sector or block that is not engaged in an Erase operation. The
operation is executed with a one-byte command sequence with Erase-Suspend command (B0H). The
device automatically enters read mode within 20 µs (max) after the Erase-Suspend command had
been issued. Valid data can be read, using a Read or Page Read operation, from any sector or block
that is not being erased. Reading at an address location within Erase-Suspended sectors or blocks will
output DQ2 toggling and DQ6 at ‘1’. While in Erase-Suspend, a Word-Program or Write-Buffer Pro-
gramming operation is allowed anywhere except the sector or block selected for Erase-Suspend.
© 2015
DS-20005015B
08/15
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SST38VF6404.PDF ] | |
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