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PDF SST49LF160C Data sheet ( Hoja de datos )
| Número de pieza | SST49LF160C | |
| Descripción | 16 Mbit LPC Flash | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Obsolete Device
Please contact Microchip Sales for replacement information.
16 Mbit LPC Flash
SST49LF160C
EOL Data Sheet
SST49LF160C flash memory device is designed to interface with host controllers
(chipsets) that support a low pin-count (LPC) interface for system firmware appli-
cations. SST49LF160C device complies with the LPC Interface Specification. The
LPC interface operates with 5 signal pins versus 32 pins of a 8-bit parallel flash
memory. This frees up pins on the ASIC host controller resulting in lower ASIC
costs and a reduction in overall system costs due to simplified signal routing.
Features
• Organized as 2M x8
• Conforms to LPC Interface Specification
– Support Single-Byte LPC Memory Read/Write Cycles
• Single 3.0-3.6V Read and Write Operations
• LPC Mode
– 5-signal LPC bus interface for both in-system and fac-
tory programming using programmer equipment
– 33 MHz clock frequency operation
– WP#/AAI and TBL# pins provide hardware Write protect
for entire chip and/or top Boot Block
– Block Locking Registers for individual block Read-Lock,
Write-Lock, and Lock-Down protection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
– Status register for End-of-Write detection
– Program-/Erase-Suspend
Read or Write to other blocks during
Program-/Erase-Suspend
• Two-cycle Command Set
• Security ID Feature
– 256-bit Secure ID space
- 64-bit Unique Factory Pre-programmed Device Identi-
fier
- 192-bit User-Programmable OTP
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 12 mA (typical)
– Standby Current: 10 µA (typical)
• Uniform 4 KByte sectors
– 35 Overlay Blocks: one 16-KByte Boot Block, two 8-
KByte Parameter Blocks, one 32-Kbyte Parameter
Block, thirty-one 64-KByte Main Blocks.
• Fast Sector-Erase/Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Program Time: 7 µs (typical)
• Auto Address Increment (AAI) for Rapid Factory
Programming (High Voltage Enabled)
– RY/BY# pin for End-of-Write detection
– Multi-Byte Program
– Chip Rewrite Time: 4 seconds (typical)
• Packages Available
– 32-lead PLCC
• All non-Pb (lead-free) devices are RoHS compliant
© 2016
www.microchip.com
DS20005099B
02/16
1 page  
Pin Assignments
16 Mbit LPC Flash
SST49LF160C
EOL Data Sheet
GPI1 (LD#)
GPI0 (RY/BY#)
WP#/AAI
TBL#
ID3
ID2
ID1
ID0
LAD0
4 3 2 1 32 31 30
5 29
6 28
7 27
8 32-lead PLCC 26
9 25
10
Top View
24
11 23
12 22
13 21
14 15 16 17 18 19 20
NC
NC
NC
NC
VDD
INIT#
LFRAME#
NC
NC
( ) Designates AAI Mode
1315 32-plcc P2.0
Figure 3: Pin Assignments for 32-lead PLCC
© 2016
DS20005099B
02/16
5
5 Page 
16 Mbit LPC Flash
SST49LF160C
LPC Memory Cycles
EOL Data Sheet
LPC Memory Read Cycle
Table 4: LPC Memory Read Cycle Field Definitions
Clock
Cycle
Field
Name
Field
Contents
LAD[3:0]1
LAD[3:0]
Direction Comments
1 START 0000
IN LFRAME# must be active (low) for the device to respond.
Only the last field latched before LFRAME# transitions high
will be recognized. The START field contents (0000b) indicate
an LPC Memory cycle.
2
CYC-
010X
TYPE +
DIR
IN Indicates the type of LPC Memory cycle. Bits 3:2 must be “01b” for
memory cycle. Bit 1 indicates the type of transfer “0” for Read. Bit 0
is reserved.
3-10 ADDR
YYYY
IN Address Phase for Memory Cycle. LPC protocol supports a
32-bit address phase. YYYY is one nibble of the entire
address. Addresses are transferred most-significant nibble
first. The SST49LF160C encodes ID and register space
access in the address fields.
11 TAR0 1111
IN In this clock cycle, the host drives the bus to all 1s and then floats
then Float the bus. This is the first part of the bus “turnaround cycle.”
12 TAR1 1111 (float) Float The SST49LF160C takes control of the bus during this cycle.
then OUT
13 RSYNC 0000
OUT
The SST49LF160C outputs the value 0000b indicating that it
has received data.
14 DATA ZZZZ
OUT ZZZZ is the least-significant nibble of the data byte.
15 DATA ZZZZ
OUT ZZZZ is the most-significant nibble of the data byte.
16 TAR0 1111
OUT, In this clock cycle, the SST49LF160C drives the bus to all 1s
then Float and then floats the bus. This is the first part of the bus “turn-
around cycle.”
17 TAR1 1111 (float) Float, The host takes control of the bus during this cycle.
then IN
1. Field contents are valid on the rising edge of the present clock cycle.
T4.0 25099
LCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
LFRAME#
LAD[3:0]
CYCTYPE
Start
+
DIR
Address
0000b 010Xb A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4]
1 Clock 1 Clock
Load Address in 8 Clocks
A[3:0]
TAR0 TAR1
Sync
Data
1111b Tri-State 0000b D[3:0] D[7:4]
2 Clocks
1 Clock Data Out 2 Clocks
Figure 4: LPC Memory Read Cycle Waveform
TAR
1315 F05.1
© 2016
DS20005099B
02/16
11
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| PDF Descargar | [ Datasheet SST49LF160C.PDF ] | |
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