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PDF KSZ8091MNX Data sheet ( Hoja de datos )
| Número de pieza | KSZ8091MNX | |
| Descripción | 10BASE-T/100BASE-TX Physical Layer Transceiver | |
| Fabricantes | Microchip | |
| Logotipo |  |
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KSZ8091MNX/RNB
10BASE-T/100BASE-TX
Physical Layer Transceiver
Features
• Single-Chip 10BASE-T/100BASE-TX IEEE 802.3
Compliant Ethernet Transceiver
• MII Interface Support (KSZ8091MNX)
• RMII v1.2 interface support with a 50 MHz refer-
ence clock output to MAC, and an option to input
a 50 MHz reference clock (KSZ8091RNB)
• Back-to-Back Mode Support for a 100 Mbps Cop-
per Repeater
• MDC/MDIO Management Interface for PHY Reg-
ister Configuration
• Programmable Interrupt Output
• LED Outputs for Link and Activity Status Indica-
tion, plus speed indication for KSZ8091RNB
• On-Chip Termination Resistors for the Differential
Pairs
• Baseline Wander Correction
• HP Auto MDI/MDI-X to Reliably Detect and Cor-
rect Straight-Through and Crossover Cable Con-
nections with Disable and Enable Option
• Auto-Negotiation to Automatically Select the
Highest Link-Up Speed (10/100 Mbps) and
Duplex (Half/Full)
• Energy Efficient Ethernet (EEE) Support with
Low-Power Idle (LPI) Mode and Clock Stoppage
(MII Version Only) for 100BASE-TX and Transmit
Amplitude Reduction with 10BASE-Te Option
• Wake-on-LAN (WOL) Support with Either Magic
Packet, Link Status Change, or Robust Custom-
Packet Detection
• HBM ESD Rating (6 kV)
• Power-Down and Power-Saving Modes
• LinkMD® TDR-Based Cable Diagnostics to Iden-
tify Faulty Copper Cabling
• Parametric NAND Tree Support for Fault Detec-
tion Between Chip I/Os and the Board
• Loopback Modes for Diagnostics
• Single 3.3V Power Supply with VDD I/O Options
for 1.8V, 2.5V, or 3.3V
• Built-In 1.2V Regulator for Core
• Available in 32-pin 5 mm x 5 mm QFN Package
Target Applications
• Game Consoles
• IP Phones
• IP Set-Top Boxes
• IP TVs
• LOM
• Printers
2016 Microchip Technology Inc.
DS00002275A-page 1
1 page  
KSZ8091MNX/RNB
2.0 PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
32-PIN 5 MM X 5 MM QFN ASSIGNMENT, KSZ8091MNX (TOP VIEW)
GND
VDD_1.2
VDDA_3.3
RXM
RXP
TXM
TXP
XO
32 31 30 29 28 27 26 25
1 24
2 23
3 22
PADDLE
4
GROUND
21
5 (ON BOTTOM OF CHIP) 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
TXD0
TXEN
TXC/PME_EN
INTRP/PME_N2/NAND_TREE#
RXER/ISO
RXC/B-CAST_OFF
RXDV/CONFIG2
VDDIO
TABLE 2-1: SIGNALS - KSZ8091MNX
Pin
Number
Pin
Name
1 GND
2 VDD_1.2
3 VDDA_3.3
4 RXM
5 RXP
Type
Note
2-1
GND
P
P
I/O
I/O
Description
Ground.
1.2V core VDD (power supplied by KSZ8091MNX)
Decouple with 2.2 µF and 0.1 µF capacitors to ground.
3.3V analog VDD
Physical receive or transmit signal (– differential)
Physical receive or transmit signal (+ differential)
2016 Microchip Technology Inc.
DS00002275A-page 5
5 Page 
KSZ8091MNX/RNB
TABLE 2-3: SIGNALS - KSZ8091RNB (CONTINUED)
Pin
Number
Pin Name
Type
Note 2-1
Description
9
XI
I
25 MHz Mode:25 MHz ±50 ppm Crystal/Oscillator/External Clock Input
50 MHz Mode: 50 MHz ±50 ppm Oscillator/External Clock Input
10 REXT
I
Set PHY transmit output current
Connect a 6.49 kΩ resistor to ground on this pin.
Management Interface (MII) Data I/O
11
MDIO
Ipu/Opu This pin has a weak pull-up, is open-drain, and requires an external 1.0 kΩ
pull-up resistor.
12
MDC
Ipu
Management Interface (MII) Clock input
This clock pin is synchronous to the MDIO data pin.
The pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of
13
PHYAD0
Ipu/O reset.
See the Strap-In Options - KSZ8091RNB section for details.
The pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of
14
PHYAD1
Ipd/O reset.
See the Strap-In Options - KSZ8091RNB section for details.
RMII mode: RMII Receive Data Output[1] (Note 2-2)
15
RXD1/
PHYAD2
Ipd/O
Config mode: The pull-up/pull-down value is latched as PHYADDR[2] at the
de-assertion of reset.
See the Strap-In Options - KSZ8091RNB section for details.
RMII mode: RMII Receive Data Output[0] (Note 2-2)
16
RXD0/
DUPLEX
Ipu/O
Config mode: The pull-up/pull-down value is latched as DUPLEX at the de-
assertion of reset.
See the Strap-In Options - KSZ8091RNB section for details.
17 VDDIO P 3.3V, 2.5V, or 1.8V digital VDD
RMII mode: RMII Carrier Sense/Receive Data Valid output
18
CRS_DV/
CONFIG2
Ipd/O
Config mode: The pull-up/pull-down value is latched as CONFIG2 at the de-
assertion of reset.
See the Strap-In Options - KSZ8091RNB section for details.
RMII mode: 25 MHz mode: This pin provides the 50 MHz RMII reference clock
output to the MAC. See also XI (pin 9).
19
REF_CLK/
B-CAST_OFF
Ipd/O
50 MHz mode: This pin is a no connect. See also XI (pin 9).
Config mode: The pull-up/pull-down value is latched as B-CAST_OFF at the
de-assertion of reset.
See the Strap-In Options - KSZ8091RNB section for details.
RMII mode: RMII Receive Error output
20
RXER/ISO
Ipd/O
Config mode: The pull-up/pull-down value is latched as ISOLATE at the de-
assertion of reset.
See the Strap-In Options - KSZ8091RNB section for details.
Interrupt output: Programmable interrupt output, with Register 1Bh as the
Interrupt Control/Status register, for programming the interrupt conditions and
reading the interrupt status. Register 1Fh, bit [9] sets the interrupt output to
active low (default) or active high.
21
INTRP/
PME_N2/
NAND_Tree#
Ipu/Opu
PME_N output: Programmable PME_N output (pin option 2). When asserted
low, this pin signals that a WOL event has occurred.
Config mode: The pull-up/pull-down value is latched as NAND Tree# at the
de-assertion of reset.
See the Strap-In Options - KSZ8091RNB section for details.
This pin has a weak pull-up and is an open-drain.
For Interrupt (when active low) and PME functions, this pin requires an exter-
nal 1.0 kΩ pull-up resistor to VDDIO (digital VDD).
2016 Microchip Technology Inc.
DS00002275A-page 11
11 Page | ||
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| PDF Descargar | [ Datasheet KSZ8091MNX.PDF ] | |
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