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PDF KSZ8794CNX Data sheet ( Hoja de datos )
| Número de pieza | KSZ8794CNX | |
| Descripción | Integrated 4-Port 10/100 Managed Ethernet Switch | |
| Fabricantes | Microchip | |
| Logotipo |  |
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KSZ8794CNX
Integrated 4-Port 10/100 Managed Ethernet
Switch with Gigabit RGMII/MII/RMII Interface
Target Applications
• Industrial Ethernet Applications that Employ IEEE
802.3-Compliant MACs. (Ethernet/IP, Profinet,
MODBUS TCP, etc.)
• VoIP Phone
• Set-Top/Game Box
• Automotive
• Industrial Control
• IPTV POF
• SOHO Residential Gateway with Full-Wire Speed
of Four LAN Ports
• Broadband Gateway/Firewall/VPN
• Integrated DSL/Cable Modem
• Wireless LAN Access Point + Gateway
• Standalone 10/100 Switch
• Networked Measurement and Control Systems
Features
• Management Capabilities
- The KSZ8794CNX Includes All the Functions
of a 10/100BASE-T/TX Switch System Which
Combines a Switch Engine, Frame Buffer
Management, Address Look-Up Table,
Queue Management, MIB Counters, Media
Access Controllers (MAC), and PHY Trans-
ceivers
- Non-Blocking Store-and-Forward Switch
Fabric Assures Fast Packet Delivery by Uti-
lizing a 1024-Entries Forwarding Table
- Port Mirroring/Monitoring/Sniffing: Ingress
and/or Egress Traffic to Any Port
- MIB Counters for Fully Compliant Statistics
Gathering (36 Counters per Port)
- Support Hardware for Port-Based Flush and
Freeze Command in MIB Counter.
- Multiple Loopback of Remote PHY, and MAC
Modes Support for the Diagnostics
- Rapid Spanning Tree Support (RSTP) for
Topology Management and Ring/Linear
Recovery
• Robust PHY Ports
- Four Integrated IEEE 802.3/802.3u-Compli-
ant Ethernet Transceivers Supporting
10BASE-T and 100BASE-TX
- IEEE 802.1az EEE Supported
- On-Chip Termination Resistors and Internal
Biasing for Differential Pairs to Reduce
Power
- HP Auto MDI/MDI-X Crossover Support Elim-
inates the Need to Differentiate Between
Straight or Crossover Cables in Applications
• MAC and GMAC Ports
- Three Internal Media Access Control (MAC1
to MAC3) Units and One Internal Gigabit
Media Access Control (GMAC4) Unit
- RGMII, MII, or RMII Interfaces Support for
the Port 4 GMAC4 with Uplink
- 2 KByte Jumbo Packet Support
- Tail Tagging Mode (One Byte Added Before
FCS) Support on Port 4 to Inform the Proces-
sor in which Ingress Port Receives the
Packet and its Priority
- Supports Reduced Media Independent Inter-
face (RMII) with 50 MHz Reference Clock
Output
- Supports Media Independent Interface (MII)
in Either PHY Mode or MAC Mode on Port 4
- LinkMD® Cable Diagnostic Capabilities for
Determining Cable Opens, Shorts, and
Length
• Advanced Switch Capabilities
- Non-Blocking Store-and-Forward Switch
Fabric Assures Fast Packet Delivery by Uti-
lizing a 1024-Entries Forwarding Table
- 64 KB Frame Buffer RAM
- IEEE 802.1q VLAN Support for up to 128
Active VLAN Groups (Full-Range 4096 of
VLAN IDs)
- IEEE 802.1p/Q Tag Insertion or Removal on
a Per Port Basis (Egress)
- VLAN ID Tag/Untag Options on Per Port
Basis
- Fully Compliant with IEEE 802.3/802.3u
Standards
- IEEE 802.3x Full-Duplex with Force-Mode
Option and Half-Duplex Back-Pressure Colli-
sion Flow Control
- IEEE 802.1w Rapid Spanning Tree Protocol
Support
- IGMP v1/v2/v3 Snooping for Multicast Packet
Filtering
2016 Microchip Technology Inc.
DS00002134A-page 1
1 page  
KSZ8794CNX
1.0 INTRODUCTION
1.1 General Description
The KSZ8794CNX is a highly integrated, Layer 2-managed, four-port switch with numerous features designed to reduce
system cost. It is intended for cost-sensitive applications requiring three 10/100 Mbps copper ports and one 10/100/
1000 Mbps Gigabit uplink port. The KSZ8794CNX incorporates a small package outline, lowest power consumption with
internal biasing, and on-chip termination. Its extensive features set includes enhanced power management, program-
mable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet fil-
tering technology, QoS priority with four queues, management interfaces, enhanced MIB counters, high-performance
memory bandwidth, and a shared memory-based switch fabric with non-blocking support. The KSZ8794CNX provides
support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit
Ethernet applications where the GMAC interface can be configured to any of RGMII, MII, and RMII modes. The
KSZ8794CNX is built on the latest industry-leading Ethernet analog and digital technology, with features designed to
offload host processing and streamline the overall design:
• Three integrated 10/100BASE-T/TX MAC/PHYs.
• One integrated 10/100/1000BASE-T/TX GMAC with selectable RGMII, MII, or RMII interfaces.
• Small 64-pin QFN package.
A robust assortment of power management features including Energy Efficient Ethernet (EEE), PME, and WoL have
been designed in to satisfy energy efficient environments.
All registers in the MAC and PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed
through the MDC/MDIO interface.
FIGURE 1-1:
FUNCTIONAL BLOCK DIAGRAM
KSZ8794
AUTO MDI/MDIX
AUTO MDI/MDIX
AUTO MDI/MDIX
SW4-RGMII/MII/RMII
MDC, MDI/O FOR MIIM
CONTROL REG SPI I/F
LED0 {3:1]
LED1 {3:1]
10/100
T/TX
EEE PHY1
10/100
T/TX
EEE PHY2
10/100
T/TX
EEE PHY3
LED I/F
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
10/100/1000
GMAC 4
SPI
CONTROL
REGISTERS
LOOK UP ENGINE
QUEUE MANAGEMENT
BUFFER MANAGEMENT
FRAME BUFFER
MIB COUNTERS
2016 Microchip Technology Inc.
DS00002134A-page 5
5 Page 
KSZ8794CNX
The KSZ8794CNX can function as a managed switch and utilizes strap-in pins to configure the device for different
modes. The strap-in pins are configured by using external pull-up/down resistors to create a high or low state on the
pins which are sampled during the power-down reset or warm reset. The functions are described in following table.
TABLE 2-2: STRAP-IN OPTIONS - KSZ8794CNX
Pin Number Pin Name
Type
(Note 2-2)
Description
19, 20
48
LED3[1,0]
LED2_1
Ipu/O
Ipu/O
Switch Port 4 GMAC4 Interface Mode Select
Strap Option:
00 = MII for SW4-MII
01 = RMII for SW4-RMII
10 = Reserved
11 = RGMII for SW4-RGMII (Default)
Port 4 MII and RMII Modes Select
Strap Option:
When Port 4 is MII mode:
PU = MAC mode.
PD = PHY mode.
When Port 4 is RMII mode:
PU = Clock mode in RMII, using 25 MHz OSC clock and provide
50 MHz RMII clock from pin RXC4.
PD = Normal mode in RMII, the TXC4/REFCLKI4 pin on the Port 4
RMII will receive an external 50 MHz clock
Note: Port 4 also can use either an internal or external clock in RMII
mode based on this strap pin or the setting of the Register 86 (0x56)
bit [7].
49
LED2_0
Ipu/O REFCLKO Enable
Strap Option:
PU = REFCLK_O (25 MHz) is enabled. (Default)
PD = REFCLK_O is disabled
50
LED1_1
Ipu/O PLL Clock Source Select
Strap Option:
PU = Still use 25 MHz clock from XI/XO pin even though it is in Port
4 RMII normal mode.
PD = Use external clock from TXC4 in Port 4 RMII normal mode.
Note: If received clock in Port 4 RMII normal mode has bigger clock
jitter, one can still select the 25 MHz Crystal/Oscillator as switch’s
clock source.
51
LED1_0
Ipu/O Port 4 Gigabit Select
Strap Option:
PU = 1 Gbps in RGMII. (Default)
PD = 10/100 Mbps in RGMII.
Note: Also programmable through internal register.
52
SPIQ
Ipd/O Serial Bus Configuration
Strap Option:
PD = SPI slave mode. (Default)
PU = MDC/MDIO mode.
Note: An external pull-up or pull-down resistor is required. If the
uplink port is used for RGMII interface, recommend using SPI mode
to have opportunity setting the register 86 (0x56) bits [4:3] for RGMII
v2.0. MDC/MDIO mode can’t set this feature.
Note 2-2
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
2016 Microchip Technology Inc.
DS00002134A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ8794CNX.PDF ] | |
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