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PDF BL24S64 Data sheet ( Hoja de datos )
| Número de pieza | BL24S64 | |
| Descripción | 64Kbits EEPROM | |
| Fabricantes | BELLING | |
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BL24S64 64Kbits (8,192×8)
Features
Compatible with all I2C bidirectional data
transfer protocol
Memory array:
– 64 Kbits (8 Kbytes) of EEPROM
– Page size: 32 bytes
Single supply voltage and high speed:
– 1 MHz （1.7V）
Random and sequential Read modes
Write:
– Byte Write within 3 ms
– Page Write within 3 ms
– Partial Page Writes Allowed
Software data Protection
Schmitt Trigger, Filtered Inputs for Noise
Suppression
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Enhanced ESD/Latch-up protection
– HBM 8000V
WLCSP4 packages
Description
The BL24S64 provides 65536 bits of serial
electrically erasable and programmable read-
only memory (EEPROM), organized as 8192
words of 8 bits each.
The device is optimized for use in many
industrial and commercial applications where
low-power and low-voltage operation are
essential.
Pin Configuration
WLCSP4
12
A Vcc
Vss
B SCL
SDA
Marking side
(top view)
BL24S64 64Kbits (8,192×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited
© 2016 Belling All Rights Reserved www.belling.com.cn
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BL24S64 64Kbits (8,192×8)
3. Device Addressing
The 64K EEPROM devices all require an 8-bit device address word following a start condition to enable
the chip for a read or write operation (see Figure 5)
The device address word consists of a mandatory "1", "0" sequence for the first four most significant
bits as shown. This is common to all the Serial EEPROM devices.
The fifth, sixth and seventh bits of the device address are set to "0".
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if
this bit is high and a write operation is initiated if this bit is low.
4. Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word
and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0"
and the addressing device, such as a microcontroller, must terminate the write sequence with a stop
condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile
memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write
is complete (see Figure 6).
PAGE WRITE: A write operation requires an 8-bit data word address following the device address word
and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0"
and the addressing device, such as a microcontroller, must terminate the write sequence with a stop
condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile
memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write
is complete (see Figure 7).
The data word address lower five bits are internally incremented following the receipt of each data
word. The higher data word address bits are not incremented, retaining the memory page row location.
When the word address, internally generated, reaches the page boundary, the following byte is placed
at the beginning of the same page. If more than 32 data words are transmitted to the EEPROM, the
data word address will "roll over" and previous data will be overwritten.
5. Software Write Protection:
A write protection operation requires a command“0xF0”following the start, and the EEPROM only
allow normal read operation. The EEPROM allows normal write/read operation when send command
“0X80”following the start (see Figure 8).
6. Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write
select bit in the device address word is set to "1". There are three read operations: current address read,
random address read and sequential read.
BL24S64 64Kbits (8,192×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited
© 2016 Belling All Rights Reserved www.belling.com.cn
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BL24S64 64Kbits (8,192×8)
Bus Timing
Figure 12. SCL: Serial Clock, SDA: Serial Data I/O
SCL
tSU.STA
tF
tLOW
tHD.STA
tHIGH
tLOW
tHD.DAT
tSU.DAT
SDA_IN
SDA_OUT
tAA
tDH
Write Cycle Timing
Figure 13. SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
Word n
ACK
tWR(1)
STOP
CONDITION
START
CONDITION
tR
tSU.STO
t BUF
Notes:
The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal
clear/write cycle.
BL24S64 64Kbits (8,192×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited
© 2016 Belling All Rights Reserved www.belling.com.cn
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