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PDF LAN9250 Data sheet ( Hoja de datos )
| Número de pieza | LAN9250 | |
| Descripción | 10/100 Industrial Ethernet Controller & PHY | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LAN9250 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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LAN9250
10/100 Industrial Ethernet Controller & PHY
Highlights
• 16-bit 10/100 industrial Ethernet controller & PHY
• Interfaces to most 8/16-bit embedded controllers
and 32-bit embedded controllers with an 8/16-bit
bus
• Integrated Ethernet PHY with HP Auto-MDIX
• Integrated Ethernet MAC
• Compliant with Energy Efficient Ethernet 802.3az
• Wake on LAN (WoL) support
• Integrated IEEE 1588v2 hardware time stamp unit
• Cable diagnostic support
• 1.8V to 3.3V variable voltage I/O
• Integrated 1.2V regulator for single 3.3V operation
• Low pin count and small body size package
Target Applications
• Cable, satellite, and IP set-top boxes
• Digital televisions & video recorders
• VoIP/Video phone systems
• Home gateways
• Test/Measurement equipment
• Industrial automation systems
Key Benefits
• Single-chip Ethernet controller
- Fully compliant with IEEE 802.3/802.3u standards
- Integrated Ethernet MAC and PHY
- 10BASE-T and 100BASE-TX support
- 100BASE-FX support for external fiber transceiver
- Automatic polarity detection and correction
(HP Auto-MDIX)
- Full- and Half-duplex support
- Full-duplex flow control
- Backpressure for half-duplex flow control
- Preamble generation and removal
- Automatic 32-bit CRC generation and checking
- Automatic payload padding and pad removal
- Loop-back modes
• Eliminates dropped packets
- Internal buffer memory can store over 200 packets
- Automatic PAUSE and back-pressure flow control
• Flexible address filtering modes
- One 48-bit perfect address
- 64 hash-filtered multicast addresses
- Pass all multicast
- Promiscuous mode
- Inverse filtering
- Pass all incoming with status report
- Disable reception of broadcast packets
• 8/16-Bit Host Bus Interface
- Indexed register or multiplexed bus
- 16Kbyte FIFO with flexible TX/RX allocation
- SPI / Quad SPI support
• IEEE 1588v2 hardware time stamp unit
- Global 64-bit tunable clock
- Ordinary clock: master / slave, one-step / two-step, end-
to-end / peer-to-peer delay
- Fully programmable timestamp on TX or RX,
timestamp on GPIO
- 64-bit timer comparator event generation (GPIO or IRQ)
• Comprehensive power management features
- 3 power-down levels
- Wake on link status change (energy detect)
- Magic packet wakeup, Wake on LAN (WoL), wake on
broadcast, wake on perfect DA
- Wakeup indicator event signal
- Link status change
• Power and I/O
- Integrated power-on reset circuit
- Latch-up performance exceeds 150mA
per EIA/JESD78, Class II
- JEDEC Class 3A ESD performance
- Single 3.3V power supply
(integrated 1.2V regulator)
• Additional Features
- Multifunction GPIOs
- General purpose timer
- Optional EEPROM interface
- Ability to use low cost 25MHz crystal for reduced BOM
• Packaging
- Pb-free RoHS compliant 64-pin QFN or 64-pin TQFP-
EP
• Available in commercial, industrial, and extended
industrial* temp. ranges
*Extended temp. (105ºC) is supported only in the 64-QFN with an
external voltage regulator (internal regulator must be disabled) and
2.5V (typ) Ethernet magnetics.
2015 Microchip Technology Inc.
DS00001913A-page 1
1 page  
LAN9250
TABLE 1-1: GENERAL TERMS (CONTINUED)
Term
Description
NRZI
N/A
NC
OUI
Outbound
PISO
PLL
PTP
RESERVED
RTC
SA
SFD
SIPO
SMI
SQE
SSD
UDP
UUID
WORD
Non Return to Zero Inverted. This encoding method inverts the signal for a “1” and
leaves the signal unchanged for a “0”
Not Applicable
No Connect
Organizationally Unique Identifier
Refers to data output from the device to the host
Parallel In Serial Out
Phase Locked Loop
Precision Time Protocol
Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaran-
teed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
Real-Time Clock
Source Address
Start of Frame Delimiter - The 8-bit value indicating the end of the preamble of an
Ethernet frame.
Serial In Parallel Out
Serial Management Interface
Signal Quality Error (also known as “heartbeat”)
Start of Stream Delimiter
User Datagram Protocol - A connectionless protocol run on top of IP networks
Universally Unique IDentifier
16 bits
2015 Microchip Technology Inc.
DS00001913A-page 5
5 Page 
LAN9250
Table 3-1 details the 64-QFN package pin assignments in table format. As shown, select pin functions may change
based on the device’s mode of operation. For modes where a specific pin has no function, the table cell will be marked
with “-”.
TABLE 3-1:
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64-QFN PACKAGE PIN ASSIGNMENTS
HBI Indexed Mode
Pin Name
HBI Multiplexed Mode
Pin Name
OSCI
OSCO
OSCVDD12
OSCVSS
VDD33
VDDCR
REG_EN
FXLOSEN
FXSDA/FXLOSA/FXSDENA
RESERVED
RST#
D2 AD2
D1 AD1
VDDIO
D14 AD14
D13 AD13
D0 AD0
PME
D9 AD9
VDDIO
D12 AD12
D11 AD11
D10 AD10
VDDCR
A1 ALELO
A3 MNGT2
A4 MNGT3
CS
A2 ALEHI
WR/ENB
RD/RD_WR
VDDIO
SPI Mode
Pin Name
SIO2
SO/SIO1
-
-
SI/SIO0
SCK
-
-
-
-
-
-
-
-
-
-
2015 Microchip Technology Inc.
DS00001913A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LAN9250.PDF ] | |
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