PDF M29W116BT Data sheet ( Hoja de datos )

Número de pieza	M29W116BT
Descripción	16 Mbit Low Voltage Single Supply Flash Memory
Fabricantes	STMicroelectronics
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M29W116BT M29W116BB 16 Mbit (2Mb x8, Boot Block) Low Voltage Single Supply Flash Memory PRELIMINARY DATA s SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS s ACCESS TIME: 70ns s PROGRAMMING TIME – 10µs by Byte typical s 35 MEMORY BLOCKS – 1 Boot Block (Top or Bottom Location) – 2 Parameter and 32 Main Blocks s PROGRAM/ERASE CONTROLLER – Embedded Byte Program algorithm – Embedded Multi-Block/Chip Erase algorithm – Status Register Polling and Toggle Bits – Ready/Busy Output Pin s ERASE SUSPEND and RESUME MODES – Read and Program another Block during Erase Suspend s TEMPORARY BLOCK UNPROTECTION MODE s SECURITY MEMORY BLOCK s UNLOCK BYPASS PROGRAM COMMAND – Faster Production/Batch Programming s LOW POWER CONSUMPTION – Standby and Automatic Standby s 100,000 PROGRAM/ERASE CYCLES per BLOCK s 20 YEARS DATA RETENTION – Defectivity below 1 ppm/year s ELECTRONIC SIGNATURE – Manufacturer Code: 20h – M29W116BT Device Code: C7h – M29W116BB Device Code: 4Ch TSOP40 (N) 10 x 20mm Figure 1. Logic Diagram VCC 21 A0-A20 8 DQ0-DQ7 W E M29W116BT M29W116BB G RB RP VSS AI02972 July 1999 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/20 1 page M29W116BT, M29W116BB Table 4. Bus Operations Operation E GW Address Inputs Data Inputs/Outputs Bus Read VIL VIL VIH Cell Address Data Output Bus Write VIL VIH VIL Command Address Data Input Output Disable X VIH VIH X Hi-Z Standby VIH X XX Hi-Z Read Manufacturer Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH 20h Read Device Code Note: X = VIL or VIH. VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH C7h (M29W116BT) 4Ch (M29W116BB) BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby and Automatic Standby. See Table 4, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not af- fect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Com- mand Interface. A valid Bus Read operation in- volves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 7, Read Mode AC Waveforms, and Table 12, Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Ad- dress Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Com- mand Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output En- able must remain High, VIH, during the whole Bus Write operation. See Figures 8 and 9, Write AC Waveforms, and Tables 13 and 14, Write AC Characteristics, for details of the timing require- ments. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data In- puts/Outputs pins are placed in the high-imped- ance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 11, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations un- til the operation completes. Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is re- duced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus opera- tions are intended for use by programming equip- ment and are not usually used in applications. They require VID to be applied to some pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 4, Bus Operations. Block Protection and Blocks Unprotection. Each block can be separately protected against acci- dental Program or Erase. Protected blocks can be unprotected to allow data to be changed. There are two methods available for protecting and unprotecting the blocks, one for use on pro- gramming equipment and the other for in-system use. For further information refer to Application Note AN1122, Applying Protection and Unprotec- tion to M29 Series Flash. 5/20 5 Page Figure 3. Data Polling Flowchart START READ DQ5 & DQ7 at VALID ADDRESS DQ7 = YES DATA NO NO DQ5 =1 YES READ DQ7 DQ7 = YES DATA NO FAIL PASS AI01369 M29W116BT, M29W116BB Figure 4. Data Toggle Flowchart START READ DQ5 & DQ6 DQ= 6 NO TOGGLE YES NO DQ5 =1 YES READ DQ6 DQ= 6 NO TOGGLE YES FAIL PASS AI01370 Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase com- mand. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read. Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Al- ternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to ad- dresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the er- ror. The Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Opera- tions from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased cor- rectly. 11/20 11 Page

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