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PDF CD4512BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4512BMS | |
| Descripción | CMOS Dual 4-Bit Latch | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CD4512BMS
December 1992
CMOS Dual 4-Bit Latch
Features
Pinout
• High-Voltage Types (20-Volt Rating)
• 3-State Outputs
• Standardized, Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V, and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and 25oC
• Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets all Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
‘B’ Series CMOS Devices"
CD4512BMS
TOP VIEW
D0 1
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
VSS 8
16 VDD
15 3-STATE DISABLE
14 SEL. OUTPUT
13 C
12 B
11 A
10 INHIBIT
9 D7
Functional Diagram
Applications
• Digital Multiplexing
• Number-sequence Generation
• Signal Gating
Description
CD4512BMS is an 8-channel data selector featuring a three-
state output that can interface directly with, and drive, data
lines of bus-oriented systems.
The CD4512BMS is supplied in these 16 lead outline
packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4S
H1E
H3X
3-STATE DISABLE
INHIBIT
10 15
D0-1
D1-2
CHANNELS
INPUTS
D2-3
D3-4
D4-5
SELECT
CONTROL
D5-6
D6-7
D7-9
A-11
B-12
C-13
CD4512BMS
14 SELECT
OUTPUT
VDD = 16
VSS = 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1180
File Number 3340
1 page  
Specifications CD4512BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
IDD
IOL5
IOH5A
± 1.0µA
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 1
Note 1
OPEN
14
GROUND
1-13, 15
VDD
16
9V ± -0.5V
50kHz
25kHz
Static Burn-In 2
Note 1
14
8 1-7, 9-13, 15, 16
Dynamic Burn-
In Note 1
-
8, 10, 15
16
14 1-7, 9, 11, 12 13
Irradiation
Note 2
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
7-1184
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CD4512BMS.PDF ] | |
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