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PDF CD4514BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4514BMS | |
| Descripción | CMOS 4-Bit Latch/4-to-16 Line Decoders | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CD4514BMS (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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December 1992
CD4514BMS
CD4515BMS
CMOS 4-Bit
Latch/4-to-16 Line Decoders
Features
Pinout
• High-Voltage Types (20-Volt Rating)
• CD4514BMS Output “High” on Select
CD4514BMS, CD4515BMS
TOP VIEW
• CD4515BMS Output “Low” on Select
• Strobed Input Latch
• Inhibit Control
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and 25oC
• Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V, and 15V Parametric Ratings
STROBE 1
DATA 1 2
DATA 2 3
S7 4
S6 5
S5 6
S4 7
S3 8
S2 9
S1 10
S0 11
VSS 12
24 VDD
23 INHIBIT
22 DATA 4
21 DATA 3
20 S10
19 S11
18 S8
17 S9
16 S14
15 S15
14 S12
13 S13
• Standardized, Symmetrical Output Characteristics
• Meets all Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
Functional Diagram
‘B’ Series CMOS Devices"
Applications
• Digital Multiplexing
• Address Decoding
• Hexadecimal/BCD Decoding
• Program-counter Decoding
• Control Decoder
Description
CD4514BMS and CD4515BMS consist of a 4-bit strobed
latch and a 4-to-16-line decoder. The latches hold the last
input data presented prior to the strobe transition from 1 to 0.
Inhibit control allows all outputs to be placed at
0(CD4514BMS) or 1(CD4515BMS) regardless of the state of
the data or strobe inputs.
VDD = 24
VSS = 12
DATA 1
DATA 2
DATA 3
DATA 4
2
3
21
22
STROBE 1
A 4 TO 16
B DECODER
LATCH C
D
INHIBIT 23
11 S0
9 S1
10 S2
8 S3
7 S4
6 S5
5 S6
4 S7
18 S8
17 S9
20 S10
19 S11
14 S12
13 S13
16 S14
15 S15
The decode truth table indicates all combinations of data
inputs and appropriate selected outputs.
These devices are similar to industry types MC14514 and
MC14515.
The CD4514BMS and CD4515BMS are supplied in these 24
lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4V
H1Z
H4P
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1188
File Number 3195
1 page  
Specifications CD4514BMS, CD4515BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 1
(Note 1)
OPEN
4-11, 13-20
GROUND
1-3, 12, 21-23
VDD
24
9V ± -0.5V
50kHz
25kHz
Static Burn-In 2
(Note 1)
4-11, 13-20
12
1-3, 21-24
Dynamic Burn-
In (Note 1)
-
2, 3, 12
21, 22, 24
4-11, 13-20
1
23
Irradiation
(Note 2)
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
7-1192
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CD4514BMS.PDF ] | |
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