DataSheetWiki


CD4518BMS fiches techniques PDF

Intersil Corporation - CMOS Dual Up Counters

Numéro de référence CD4518BMS
Description CMOS Dual Up Counters
Fabricant Intersil Corporation 
Logo Intersil Corporation 





1 Page

No Preview Available !





CD4518BMS fiche technique
CD4518BMS,
CD4520BMS
December 1992
CMOS Dual Up Counters
Features
Pinout
• High Voltage Types (20V Rating)
• CD4518BMS Dual BCD Up Counter
• CD4520BMS Dual Binary Up Counter
• Medium Speed Operation
- 6MHz Typical Clock Frequency at 10V
• Positive or Negative Edge Triggering
• Synchronous Internal Carry Propagation
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
CD4518BMS, CD4520BMS
TOP VIEW
CLOCK A 1
ENABLE A 2
Q1A 3
Q2A 4
Q3A 5
Q4A 6
RESET A 7
VSS 8
16 VDD
15 RESET B
14 Q4B
13 Q3B
12 Q2B
11 Q1B
10 ENABLE B
9 CLOCK B
Functional Diagram
Applications
• Multistage Synchronous Counting
• Multistage Ripple Counting
• Frequency Dividers
Description
CD4518BMS Dual BCD Up Counter and CD4520BMS Dual
Binary Up Counter each consist of two identical, internally
synchronous 4-stage counters. The counter stages are
D-type flip-flops having interchangeable CLOCK and
ENABLE lines for incrementing on either the positive-going
or negative-going transition. For single unit operation the
ENABLE input is maintained high and the counter advances
on each positive-going transition of the CLOCK. The
counters are cleared by high levels on their RESET lines.
The counter can be cascaded in the ripple mode by connect-
ing Q4 to the enable input of the subsequent counter while
the CLOCK input of the latter is held low.
CLOCK A
1
ENABLE A
2
RESET A
7
CLOCK B
9
ENABLE B
10
RESET B
15
÷10/÷16
C
R
3
Q1A
4
Q2A
5
Q3A
6
Q4A
÷10/÷16
C
R
11
Q1B
12
Q2B
13
Q3B
14
Q4B
The CD4518BMS and CD4520BMS are supplied in these
16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4518B Only
H4S
H1F
*H6P †H6W
†CD4520B Only
VSS = 8
VDD = 16
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1206
File Number 3342

PagesPages 10
Télécharger [ CD4518BMS ]


Fiche technique recommandé

No Description détaillée Fabricant
CD4518BMS CMOS Dual Up Counters Intersil Corporation
Intersil Corporation

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche