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PDF ADuCM322 Data sheet ( Hoja de datos )
| Número de pieza | ADuCM322 | |
| Descripción | Precision Analog Microcontroller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Precision Analog Microcontroller, Analog I/O
with MDIO Interface, ARM Cortex-M3
ADuCM322
FEATURES
Analog input/output
Multichannel, 12-bit, 1 MSPS analog-to-digital
converter (ADC)
Up to 16 ADC input channels
0 V to VREF analog input range
Single-ended modes
AVDD and IOVDD monitors
12-bit voltage output digital-to-analog converters (VDACs)
8 VDACs with a range of 0 V to 2.5 V or AVDD outputs
Voltage comparator
Microcontroller
ARM Cortex-M3 processor, 32-bit RISC architecture
Serial wire port supports code download and debug
Clocking options
80 MHz phase-locked loop (PLL) with programmable divider
Trimmed on-chip oscillator (±3%)
External 16 MHz crystal option
External clock source up to 80 MHz
Memory
2 × 128 kB independent Flash/EE memories
10,000 cycle Flash/EE endurance
20-year Flash/EE retention
32 kB SRAM
Software triggered in-circuit reprogrammability via
management data input/output (MDIO)
On-chip peripherals
MDIO slave up to 4 MHz
2 × I2C, 2 × SPI, UART
Multiple general-purpose input/output (GPIO) balls: 3.6 V
compliant
7 × 1.2 V compatible when used for MDIO
32-element programmable logic array (PLA)
3 general-purpose timers
Wake-up timer
Watchdog timer
16-bit pulse width modulator (PWM)
Power
Supply range: 2.9 V to 3.6 V
Flexible operating modes for low power applications
Packages and temperature range
6 mm × 6 mm, 96-ball CSP_BGA package
Fully specified for −40°C to +105°C ambient operation
Tools
QuickStart development system
Full third-party support
APPLICATIONS
Optical networking
FUNCTIONAL BLOCK DIAGRAM
BUF_VREF2V5
XTALO XTALI ECLKIN
AIN0
AIN5
AIN6
AIN15
VDAC0
VDAC7
2.5V BAND GAP
1.8 V LDO
MUX
SAR ADC
CLOCK SYSTEM
32.768kHz
16MHz OSC
80MHz PLL
INTERNAL
CHANNELS:
TEMPERATURE,
AVDD, IOVDD
COMPARATOR
VDAC
VDAC
ADuCM322
ARM
CORTEX-M3
PROCESSOR
MEMORY
2 × 128kB FLASH
32kB SRAM
DMA
NVIC
RESET SYSTEM
GPIO PORTS
UART
2 × SPI
2 × I2C
EXT IRQS
MDIO
PLA
3 × GP TIMER
WD TIMER
WAKE-UP TIMER
PWM
SERIAL WIRE
DGNDx
AVDDx
AGNDx
IOVDDx
IOGNDx
GENERAL
PURPOSE
I/O PORTS
PWM0 TO
PWM6
SWDIO
SWCLK
RESET
Figure 1.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADuCM322
Data Sheet
SPECIFICATIONS
MICROCONTROLLER ELECTRICAL SPECIFICATIONS
AVDD = IOVDD = VDD1 = 2.9 V to 3.6 V (see Figure 12), maximum difference between supplies = 0.3 V, VREF = 2.5 V internal reference,
fCORE = 80 MHz, TA = −40°C to +105°C, unless otherwise noted. The power-up sequence must be VDD1, IOVDDx, and AVDDx, but no
delays in the sequence are required.
Table 1.
Parameter
ADC BASIC SPECIFICATIONS
ADC Power-Up Time
Data Rate
DC Accuracy1
Resolution1
Integral Nonlinearity
Symbol Min
fSAMPLE
INL
12
16
Differential Nonlinearity
DNL −0.99
DC Code Distribution
ADC ENDPOINT ERRORS
Offset Error
Drift1
Match
Full-Scale Error
Gain Drift1
−3.92
−4
Match
ADC DYNAMIC PERFORMANCE
Signal-to-Noise Ratio
SNR
Total Harmonic Distortion
THD
Peak Harmonic or Spurious Noise
Channel-to-Channel Crosstalk
ADC INPUT
Input Voltage Ranges
Single-Ended Mode1
AGND
Compliance1
AGND4
Leakage Current
Input Current
Input Capacitance
ON-CHIP VOLTAGE REFERENCE
Accuracy
Reference Temperature Coefficient1
Power Supply Rejection Ratio
Internal VREF Power-On Time
PSRR
Typ Max
5
1
±1.75
±1.75
±0.75
±0.75
±3
±200
0.3
±1
±400
±1
80
−86
−88
−90
+1.5
+1.21
+5
VREF
AVDD4
±1.5
±9
±6
±4
20
2.51
±5
±15
60
50
Unit
µs
MSPS
Bits
Bits
LSB
LSB
LSB
LSB
LSB
µV
µV/°C
LSB
µV
µV/°C
LSB
dB
dB
dB
dB
Test Conditions/Comments
Single-ended mode, unless
otherwise stated
1 LSB = 2.5 V/212
Number of data bits
2.5 V internal reference; 1 LSB =
2.5 V/212
2.5 V external reference; 1 LSB =
2.5 V/212
2.5 V internal reference; 1 LSB =
2.5 V/212
2.5 V external reference; 1 LSB =
2.5 V/212
ADC input 1.25 V; 1 LSB = 2.5 V/212
Using 2.5 V external reference
Matching compared to AIN8
Full-scale error drift minus offset
error drift
fIN = 665.25 Hz sine wave, fSAMPLE =
100 kSPS; input filter = 15 Ω, CL = 2 nF
Includes distortion and noise
components
Measured on adjacent channels
nA
µA/V
µA/V
µA/V
pF
V
mV
ppm/°C
dB
ms
At 1 MSPS
≤800 kSPS
500 kSPS, ADCCNVC, Bits[25:16] =
0x1E
During ADC acquisition
0.47 µF from VREF_1V2 to AGND4;
reference is measured with all ADC
and VDACs enabled
TA = 25°C
Rev. 0 | Page 4 of 23
5 Page 
ADuCM322
Table 5. SPI Master Mode Timing (Phase Mode = 0)
Parameter
Description
tSL SCLK low pulse width
tSH SCLK high pulse width
tDAV Data output valid after SCLK edge
tDOSU Data output setup before SCLK edge
tDSU Data input setup time before SCLK edge
tDHD Data input hold time after SCLK edge
tDF Data output fall time
tDR Data output rise time
tSR SCLK rise time
tSF SCLK fall time
Min
0
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
MOSI
tSH
tSL
tDOSU
MSB
tDAV
tDF
tDR
BITS 6 TO 1
Data Sheet
Typ
(SPIDIV + 1) × tHCLK/2
(SPIDIV + 1) × tHCLK/2
3
½ SCLK
SCLK
SCLK
25
25
20
20
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSR tSF
LSB
MISO
MSB IN
BITS 6 TO 1
LSB IN
tDSU
tDHD
Figure 4. SPI Master Mode Timing (Phase Mode = 0)
Rev. 0 | Page 10 of 23
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ADuCM322.PDF ] | |
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