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PDF CD4556BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4556BMS | |
| Descripción | CMOS Dual Binary to 1 of 4 Decoder/Demultiplexers | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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December 1992
CD4555BMS
CD4556BMS
CMOS Dual Binary to 1 of 4
Decoder/Demultiplexers
Features
• High Voltage Type (20V Rating)
• CD4555BMS: Outputs High on Select
• CD4556BMS: Outputs Low on Select
• Expandable with Multiple Packages
• 100% Tested for Quiescent Current at 20V
• Standardized, Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Decoding
• Code Conversion
• Demultiplexing (Using Enable Input as a Data Input
• Memory Chip-Enable Selection
• Function Selection
Description
CD4555BMS and CD4556BMS are dual one-of-four decod-
ers/demultiplexers. Each decoder has two select inputs (A
and B), an Enable input (E), and four mutually exclusive out-
puts. On the CD4555BMS the outputs are high on select; on
the CD4556BMS the outputs are low on select.
When the Enable input is high, the outputs of the
CD4555BMS remain low and the outputs of the
CD4556BMS remain high regardless of the state of the
select inputs A and B. The CD4555BMS and CD4556BMS
are similar to types MC14555 and MC14556, respectively.
The CD4555BMS and CD4556BMS are supplied in these
16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4555B Only
*H46 †H4T
H1E
H6W
†CD4556B Only
Pinouts
CD4556BMS
TOP VIEW
E1
A2
B3
1/2 OF DUAL Q0 4
Q1 5
Q2 6
Q3 7
VSS 8
16 VDD
15 E
14 A
13 B
12 Q0 1/2 OF DUAL
11 Q1
10 Q2
9 Q3
CD4555BMS
TOP VIEW
E1
A2
B3
1/2 OF DUAL Q0 4
Q1 5
Q2 6
Q3 7
VSS 8
16 VDD
15 E
14 A
13 B
12 Q0 1/2 OF DUAL
11 Q1
10 Q2
9 Q3
Functional Diagrams
VDD 16
A
B
2
3
E1
A 14
B 13
E 15
VSS 8
4 Q0
5 Q1
6 Q2
7 Q3
12 Q0
11 Q1
10 Q2
9 Q3
CD4555BMS
VDD 16
A
B
2
3
E1
A 14
B 13
E 15
4 Q0
5 Q1
6 Q2
7 Q3
12 Q0
11 Q1
10 Q2
9 Q3
VSS 8
CD4556BMS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1249
File Number 3346
1 page  
Specifications CD4555BMS, CD4556BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
PART NUMBER CD4555BMS & CD4556BMS
Static Burn-In 1
Note 1
4 - 7, 9 - 12
1 - 3, 8, 13 - 15
16
Static Burn-In 2
Note 1
4 - 7, 9 - 12
8 1 - 3, 13 - 16
Dynamic Burn-
In Note 1
-
1, 8, 15
16
4 - 7, 9 - 12
2, 14
3, 13
Irradiation
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagrams
2(14)
A
*
3(13)
B
*
1(15)
E
*
*ALL INPUTS PROTECTED BY CMOS
PROTECTION NETWORK
4(12)
Q0
5(11)
Q1
6(10)
Q2
7(9)
Q3
VDD
2(14)
A
*
3(13)
B
*
1(15)
E
*
*ALL INPUTS PROTECTED BY CMOS
PROTECTION NETWORK
4(12)
Q0
5(11)
Q1
6(10)
Q2
7(9)
Q3
VDD
VSS
FIGURE 1. CD455RBMS LOGIC DIAGRAM (1 OF 2 IDENTICAL
CIRCUITS)
VSS
FIGURE 2. CD4556BMS LOGIC DIAGRAM (1 OF 2 IDENTICAL
CIRCUITS)
7-1253
5 Page 
CD4555BMS, CD4556BMS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
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1130 Brussels, Belgium
TEL: (32) 2.724.2111
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ASIA
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Taiwan Limited
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Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
1259
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| PDF Descargar | [ Datasheet CD4556BMS.PDF ] | |
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