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PDF TC511632FTL-10 Data sheet ( Hoja de datos )
| Número de pieza | TC511632FTL-10 | |
| Descripción | SILICON GATE CMOS PSEUDO STATIC RAM | |
| Fabricantes | Toshiba | |
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TOSHIBA
SILICON GATE CMOS
1l:511632~/F1lL-70/85/10
PRELIMINARY
32,768 WORD x 16 BIT CMOS PSEUDO STATIC RAM
Description
The TC511632FUFTL is a 512K bit high speed CMOS pseudo static RAM organized as 32,768 words by 16 bits. The
TC511632FUFTL utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high
speed and low power storage. The TC511632FUFTL operates from a single 5V power supply. Refreshing is supported by a
refresh (RFSH) input which enables two types of refreshing - auto refresh and self refresh. The TC511632FUFTL features a static
RAM-like interface with a write cycle in which the input data is written into the memory cell at the rising edge of WE thus simplifying
the microprocessor interface.
The TC511632FUFTL is available in a 40-pin small outline plastic flat package and a 44-pin outline (40 actual pins) plastic thin
small outline package (forward type).
Features
Pin Connection (Top View)
• Organization: 32,768 words x 16 bits
• Single 5V power supply
• Fast access time
TC511632FL/FTL
-70 -85 -10
tCEA CE Access Time
tOEA OE Access Time
tAC Cycle Time
Power Dissipation
Self Refresh Current
70ns
30ns
115ns
440mW
85ns
35ns
135ns
385mW
100!lA
100ns
40ns
160ns
330mW
• Auto refresh is supported by an internal refresh address
counter
GND
A9
A8
A7
A6
AS
A4
A3
A2
Al
AO
1/01
1/02
1103
1/04
1/05
1/06
1107
1/08
GND
imr GND
A9
"['i;ii;iE
A8
Al0 A7
All A6
A12 AS
An A4
Al.l1Q4! __
A3
A2
l.QEI RFSH Al
CE
1/016
1/015
AO
1/014
1/013
11012
11011
1/01
1102
1103
1104
1/010 1105
1109 1106
Voo 1/07
FL
1/08
GND
twr
lWE
AIO
All
Al2
A13
\A.!1i4ll __
LOE I RFSH
'IT
1/016
11015
11014
11013
11012
11011
11010
1/09
Voo
FTL
• Self refresh is supported by an internal timer
• Inputs and outputs TIL compatible
• Refresh: 256 refresh cycles/4ms
• Package
- TC511632FL: SOP40-P-525
- TC511632FTL: TSOP44-P-400B
Pin Names
AO - A14
UWE
Address Inputs
Upper Byte Write Enable Input
LWE
Lower Byte Write Enable Input
UOE
Upper Byte Output Enable Input
LOE/RFSH
CE
Lower Byte Output Enable Input
Refresh Input
Chip Enable Input
1/01 - 1/016
VDD
GND
Data Inputs/Outputs
Power
Ground
TOSHIBA AMERICAEL.ECTRONIC COMPDNENTS, INC.
0-19
1 page  
Static RAM
TC511632FUFTL-70/8511 0
Notes:
1) Stress greater than those listed under "Maximum Ratings" may cause permanent damage to the device.
2) All voltages are referenced to GND.
3) 1000 depends on the cycle time.
4) 1000 depends on the output loading. Specified values are obtained with the outputs open.
5) An initial pause of 100llS with high CE is required after power-up before proper device operation is achieved.
6) AC measurements assume tT = 5ns.
7) Timing reference levels
Input Levels
Input Reference Levels
Output Reference Levels
V1H
V1L
= 2.6V
=0.6V
V1H = 2.4V
V1L =0.8V
VOH = 2.2V
VOL = 0.8V
INPUT
2.6V
O.6V
OUTPUT
INPUT REFERENCE
LEVEL
2.2V
OUTPUT REFERENCE
LEVEL
8) Measured with a load equivalent to 1 TIL load and 100pF.
9) tCHZ, tOHZ' tWHZ define the time at which the output achieves the open circuit condition and is not referenced to output
voltage levels.
10) For write cycles, the input data is latched at the earlier of WE or CE rising edge. Therefore, the input data must be valid
during the setup time (tosw or toscl and hold time (tOHW or tOHcl.
11) All address inputs,are latched at the falling edge of CEo Therefore, all the address inputs must be valid during tASC and tAHC '
12) The two refresh operations, auto refresh and self refresh, are defined by the RFSH pulse width under the condition CE ::: V1H.
Auto refresh : RFSH pulse width ~ tFAP (max.)
Self refresh : RFSH pulse width ~ tFAS (min.)
The timing parameter tFRs must be met for proper device operation under the following conditions:
• after self refresh
• if RFSH = ilL" after power-up
13) CE only refresh or auto refresh must begin within 15.61lS after self refreshing ends.
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
0-23
5 Page 
Upper Byte Read Modify Write Cycle
Static RAM
TC511632FUFTL-70/85/10
VIH
AO - A14 Vil
V1H -
U'OE Vil _ ~--------------------------++------~--------------------~~----------------------------------------~-------------------------------
'[QEiRFSHV1H
-
_
V'l ~--------------------------++------~--------------------~~----------------------------------------~-------------------------------
VIH _:-----=t:RC:S:~t:~-+---4-~-------!-J I0Il1--"';';';"'-'-+1 .u----!-'~~rI_-----
Vil -;...-_ _ _ _J
V1H _~--~==t=RC=S ~~~--~~----------~4J~------~----~~~~---------
V1l -;...-_ _ _ _J
V 1H
Vil
_- --------+-+--+-+-------.....-4-4----lt'-_~--....-~
1/09-1/016
LOUT VVOOH- L----Hz----~---+~-~
HZ
~N
VIH
VIL
-_--------~-~~------r---------------------
1/01-1/08
LOUT VVOOHL- ---H-z----~-----~
1/01-8: DIN = "W or "L"
• : "H" or -L"
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS. INC.
0-29
11 Page | ||
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