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PDF TC518128BPL-70V Data sheet ( Hoja de datos )
| Número de pieza | TC518128BPL-70V | |
| Descripción | SILICON GATE CMOS PSEUDO STATIC RAM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TOSHIBA
SILICON GATE CMOS
TC518l28BPL/BFL/BFWL/BFIL-70V/80V/lOV
131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM
Description
The TC518128B-V is a 1M bit high speed CMOS pseudo static RAM organized as 131,072 words by 8 bits. The TC518128B-V
utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed and low power
storage. The TC518128B-Voperates from a single power supply of 2.7 - 5.5V. Refreshing is supported by a refresh (RFS~ input
which enables two types of refreshing - auto refresh and self refresh. The TC518128B-V features a static RAM-like interface with a
write cycle in which the input data is written into the memory cell at the rising edge of RMI thus simplifying the microprocessor
interface.
The TC518128B-V is pin-compatible with the 1M bit CMOS static RAM JEDEC standard and is available in a 32-pin, 0.6 inch
width plastic DIP, a small outline plastic flat package, and a 32-pin thin small outline plastic package (forward type).
Features
Pin Connection (Top View)
• Organization:
131,072 words x 8 bits
• Low voltage operation
2.7V - 5.5V
• Data retention supply voltage: 2.7V - 5.5V
• Fast access time
TC518128B-V Family
-70 -80 -10
tCEA CE Access Time
tOEA OE Access Time
tRc Cycle Time
Power Dissipation
Self Refresh Current 1 5.5V
1 3.OV
70ns
25ns
115ns
385mW
SOns
30ns
130ns
330mW
50J.lA
25J.lA
100ns
40ns
160ns
275mW
FsH
A16
A14
A12
A7
A6
AS
A4
A3
A2
Al
AO
1101
1102
1103
GNO
~~~
CE2
RIW
A13
A8
A9
All
OE
AlP
Ce1
1108
1107
1106
1105
1/04
TC518128BPL/BFL/BFVVl
'li 1O 3
:
16 17
TC518128BFTL ( Forward)
• Auto refresh is supported by an internal refresh address
counter
• Self refresh is supported by an internal timer
• Inputs and outputs TTL compatible
• Refresh: 512 refresh cycles/8ms
• Auto refresh power down feature
• Pin compatible: 1M SRAM (JEDEC)
• Package
- TC518128BPL: DIP32-P-600
- TC518128BFL: SOP32-P-450
- TC518128BFWL: SOP32-P-525
- TC518128BFTL: TSOP32-P-0820
Pin Names
AO - A16
R/W
OE
RFSH
CE1, CE2
1/01 - 1/08
Voo
GND
Address Inputs
Read/Write Control Input
Output Enable Input
Refresh Input
Chip Enable Inputs
Data InputslOutputs
Power
Ground
(TSOP)
PIN NO. 1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16
PIN NAME A11 Ag As A13 R/W CE2 A1S Voo RFSH A16 A14 A12 A7 A6 As A4
PIN NO. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN NAME A3 A2 A1 Ao 1/01 1/02 1/03 GND 1/04 1/05 1/06 1/07 1/08 CE1 A10 OE
TOSHIBA AMERICA ELECTRONIC CDMPDNENTS, INC.
0-67
1 page  
Static RAM
TC518128BPUBFUBFWUBFTL·70Vl80Vl1 OV
3.0V Operation
DC Recommended Operating Conditions
SYMBOL
PARAMETER
Voo
V 1H
V 1L
Power Supply Voltage
Input High Voltage
Input Low Voltage
MIN.
2.7
Voo - 0.2V
-0.5
TYP. MAX. UNIT NOTES
3.0 3.3
- Voo + 1.0V
- 0.2
V
V
V
2
DC Characteristics (Ta =0 - 70°C, Voo =3.0V±O.3V)
SYMBOL
PARAMETER
1000
100S2
100F2
100F3
100F4
II(L)
10(L)
VOH
VOL
Operating Current (Average)
=CE1, CE2, Address cycling: tRc tRC min.
Standby Current
Self Refresh Current (Average)
Auto Refresh Current (Average)
=RFSH cycling: tFc tFG min
CE only Refresh Current (Average)
=CE1, CE2, Address cycling: tRG tRG min.
Input Leakage Current
=OV::; V1N ::; V oo, All other Inputs not under test OV
Output Leakage Current
Output Disable, OV::; VOUT ::; Voo
Output High Level
10H =-1mA
=10H -100~
Output Low Level
10L =2.1mA
10L = 100/lA
MIN. TYP. MAX.
- 15 20
- 15 25
- 15 25
- -2
- 15 20
- - ±10
-
2.4
Voo - O.2V
-
-
-
-
-
-
-
±10
-
-
0.4
0.2
UNIT NOTES
rnA 3,4
~
~
rnA
rnA 3
~
~
V
V
TOSHIBA AMERICA ELECTRONIC COMPONENTS. INC.
D·71
5 Page 
Read Modify Write Cycle
Static RAM
TC518128BPUBFUBFWUBFTl-70Vl80Vl10V
CE2
VIH -
M
V1L -
V1H -
R/VII VIL -
r N ~:~ =--------+-+--+-+_-----+--h----<J,,___~~~~::~------
LV01-V08
OUT VVOOHL- ---------~~-+--~
________________ __ _______~VIVLIH --~______~~========~========~~
~~ ~~
CE Only Refresh
m VIH -
VIL -
CE2
VIH
AO- A8 V1L
VIH -
M
VIL -
VIH -
RIW
VIL -
VOH-
I/Ol-VOS VOL-
~VIV1LH --
=Note: A9 - A 16 V1H or V1L
tFRS
Note: The device can be operated by cycling CE1 (or CE2) only provided that CE2 (or CE1) is connected to V1H (or V1U.
~:HorL
TOSHIBA AMERICA ELECTRONIC COMPONENTS. INC.
0-77
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet TC518128BPL-70V.PDF ] | |
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