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PDF TC55V1664J-15 Data sheet ( Hoja de datos )

Número de pieza TC55V1664J-15
Descripción 16-Bit CMOS SRAM
Fabricantes Toshiba 
Logotipo Toshiba Logotipo



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No Preview Available ! TC55V1664J-15 Hoja de datos, Descripción, Manual

TOSHIBA
1l:5~1664J/F1l-10/12/15
SILICON GATE CMOS
PRELIMINARY
65,536 WORD x 16 BIT CMOS STATIC RAM
Description
The TC55V1664J/FT is a 1,048,576 bit high speed CMOS static random access memory organized as 65,536 words by 16 bits
and operated from a single 3.3V supply. Toshiba's advanced CMOS technology and circuit design enable hJgtl speed operation.
The TC55V1664J/FT features low power dissipation when the device is deselected using chip enable (CE), and has an output
enable input (OE) for fast memory access. Byte access is supported by upper and lower byte controls.
The TC55V1664J/FT is suitable for use in high speed applications such as cache memory and high speed storage. All inputs and
outputs are LVTTL compatible.
The TC55V1664J/FT is available in a 400mil width, 44-pin plastic SOJ and thin small outline package (forward type) suitable for
high density surface assembly.
Features
• Fast access time
- TC55V1664J/FT -10
- TC55V1664J/FT -12
- TC55V1664J/FT -15
10ns (max.)
12ns (max.)
15ns (max.)
Cycle Time
Operation (max.)
- Standby:
1mA (max.)
• Single 3.3V power supply: 3.3V±0.3V
• Fully static operation
• Inputs and outputs LVTTL compatible
• Output buffer control:
OE
• Data byte controls:
LB,UB
• Package
- TC55V1664J: SOJ44-P-400
- TC55V1664FT: TSOP44-P-400
Pin Names
AD -A15
1/01 - 1/016
CE
WE
OE
LB, UB
Voo
GND
NC
NU*
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Data Byte Control Inputs
Power (+3.3V)
Ground
No Connection
Not Usable (Input)
Pin Connection (Top View)
TC55V1664J
A4
A3
A2
A1
AaO
1/01
1/02
1/03
1/04
Voo
GND
1/05
1/06
1/07
1/08
WE
A15
A14
A13
A12
NC
(50J)
AS
A6
A7
OE
UB
LB
1/016
1/015
1/014
1/013
GND
Voo
1/012
1/011
1/010
1/09
NU
A8
A9
Al0
Al'
NC
A4
A3
A2
A1
AO
CE
1/01
1/02
1/03
1/04
Voo
GND
1/05
1/06
1/07
1/08
WE
A15
A14
A13
A12
NC
* The NU pin must be kept electronically open, pulled down to GND, or less
than a.8V. Applying a voltage greater than a.8V to the NU pin is prohibited.
TCSSV1664FT
10 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 36
10 35
11 34
12 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
(T50P)
AS
A6
A7
OE
UB
LB
1/016
1/015
1/014
1/013
GND
Voo
1/012
1/011
1/010
1/09
NU
A8
A9
AIO
Al'
NC
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
8-129

1 page




TC55V1664J-15 pdf
Timing Waveforms
Read Cycle (2)
ADDRESSES
Static RAM
TC55V1664J/FT-10/12115
Oout--------------~----------~
Write Cycle 1 (5) (WE Controlled)
ADDRESSES
Hi9h Impedance
Din
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
8-133

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