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TC55V1864J-15 Datasheet دیتاشیت PDF دانلود

دیتاشیت - Toshiba - 18-Bit CMOS SRAM

شماره قطعه TC55V1864J-15
شرح مفصل 18-Bit CMOS SRAM
تولید کننده Toshiba 
آرم Toshiba 


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TC55V1864J-15 شرح
TOSHIBA
1l:55\T1864J/F1l-10/12/15
SILICON GATE CMOS
PRELIMINARY
65,536 WORD x 18 BIT CMOS STATIC RAM
Description
The TC55V1864J/FT is a 1,179,648 bit high speed CMOS static random access memory organized as 65,536 words by 18 bits
and operated from a single 3.3V supply. Toshiba's advanced CMOS technology and circuit design enable hJ9!:l speed operation.
The TC55V1864J/FT features low power dissipation when the device is deselected using chip enable (CE), and has an output
enable input (OE) for fast memory access. Byte access is supported by upper and lower byte controls.
The TC55V1864J/FT is suitable for use in high speed applications such as cache memory and high speed storage. All inputs and
outputs are LVTTL compatible.
The TC55V1864J/FT is available in a 400mil width, 44-pin plastic SOJ and thin small outline package (forward type) suitable for
high density surface assembly.
Features
• Fast access time
- TC55V1864J/FT -10
- TC55V1864J/FT -12
- TC55V1864J/FT -15
• Low power dissipation
10ns (max.)
12ns (max.)
15ns (max.)
Cycle Time
10
Operation (max.)
- Standby:
1mA (max.)
• Single 3.3V power supply: 3.3V±O.3V
• Fully static operation
• Inputs and outputs LVTTL compatible
• Output buffer control:
OE
• Data byte controls:
LB,UB
• Package
- TC55V1864J: SOJ44-P-400
- TC55V1864FT: TSOP44-P-400
Pin Names
AO - A15
1/01 - 1/018
CE
WE
OE
LB, UB
VDD
GND
NU*
Address Inputs
Data InputS/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Data Byte Control Inputs
Power (+3.3V)
Ground
Not Usable (Input)
Pin Connection (Top View)
TCSSV1864J
A4
A3
A2
Al
AO
IT
1/01
1/02
1/03
1/04
Voo
GND
1105
1/06
1/07
1/08
1109
WE
A15
A14
A13
A12
(50J)
A5
A6
A7
OE
US
LB
1/018
11017
1/016
1/015
GND
Voo
1/014
1/013
11012
1/011
11010
NU
A8
A9
Al0
All
A4
A3
A2
Al
AO
CE
1/01
1/02
1/03
1/04
Voo
GND
1/05
1/06
1/07
1/08
1/09
WE
A15
A14
A13
A12
TCS5V1864FT
0
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 36
10 35
11 34
12 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 2S
21 24
22 23
(T50P)
AS
A6
A7
OE
US
LB
1/018
1/017
1/016
1/015
GND
Voo
1/014
1/013
1/012
1/011
1/010
NU
AS
A9
Al0
All
* The NU pin must be kept electronically open, pulled down to GND, or
less than O.BV. Applying a voltage greater than O.BV to the NU pin is
prohibited.
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
8-137

قانون اساسیصفحه 7
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