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TC554101J-30 fiches techniques PDF

Toshiba - 4-Bit Separate I/O CMOS SRAM

Numéro de référence TC554101J-30
Description 4-Bit Separate I/O CMOS SRAM
Fabricant Toshiba 
Logo Toshiba 





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TC554101J-30 fiche technique
TOSHIBA
112554101]-20/25/30
SILICON GATE CMOS
1,048,576 WORD x 4 BIT SEPARATE 1/0 CMOS STATIC RAM
PRELIMINARY
Description
The TC5541 01 J is a 4,194,304 bit high speed CMOS static random access memory organized as 1,048,576 words by 4 bits and
operated from a single 5V supply. Toshiba's advanced CMOS technology and circuit design enable hi~peed operation.
The TC5541 01 J features low power dissipation when the device is deselected using chip enable (CE), and has an output
enable input (OE) for fast memory access.
The TC5541 01 J is suitable for use in applications where high speed is required such as cache memory, high speed storage, and
main memory. All inputs and outputs are TTL compatible.
The TC5541 01 J is available in a 400mil width, 36-pin SOJ suitable for high density surface assembly.
Features
• Fast access time
- TC5541 01 J -20 20ns (max.)
- TC5541 01 J -25 25ns (max.)
- TC5541 01 J -30 30ns (max.)
• Low power dissipation
- TC5541 01 J -20 160mA (max.)
- TC5541 01 J -25 160mA (max.)
- TC5541 01 J -30 150mA (max.)
- Standby:
1OmA (max.)
• Single 5V power supply: 5V±10%
• Fully static operation
• Inputs and outputs TTL compatible
• Separate inputs and outputs
• Output buffer control: OE
• Package:
- TC5541 01 J:
SOJ36-P-400
Pin Names
AO - A19
D1 - D4
01 - 04
CE
WE
OE
VDD
GND
TF*
Address Inputs
Data Inputs
Data Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power (+5V)
Ground
Test Function
Pin Connection (Top View)
AO
Al
A2
A3
A4
IT
01
Q1
Voo
GNO
Q2
02
WE
AS
A6
Al
A8
A9
A19
A18
All
A16
A15
OE
04
Q4
GNO
VDD
Q3
03
TF
A14
A 13
A12
All
A10
* The TF pin is low for normal operation.
TOIt:U"tII:lA AMI:RI~A I:LI:CTAONIC COMPONENTS. INC.
8-151

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