PDF MCM6726 Data sheet ( Hoja de datos )

Número de pieza	MCM6726
Descripción	128K x 8 Bit Fast Static Random Access Memory
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA • SEMICONDUCTOR TECHNICAL DATA 128K X 8 Bit Fast Static Random Access Memory The MCM6726 is a 1,048,576 bit static random access memory organized as 131,072 words of 8 bits. This device is fabricated using high performance silicon-gate SiCMOS technology. Static design eliminates the need for external clocks or timing strobes. Output enable (G) is a special control feature that provides increased system flexi- bility and eliminates bus contention problems. This device meets JEDEC standards for functionality and revolutionary pinout, and is available in a 400 mil plastic small-outline J-Ieaded package. • Single 5 V ± 10% Power Supply • Fully Static - No Clock or Timing Strobes Necessary • All Inputs and Outputs Are TTL Compatible • Three State Outputs • Fast Access Times: 10, 12, 15 ns • Center Power and I/O Pins for Reduced Noise BLOCK DIAGRAM MEMORY ··• MATRIX 512 ROWS x2S6 x 8 COLUMNS Vee VSS MCM6726 ~JPACKAGE E400MILSOJ CASE 857A PIN ASSIGNMENT AA AA AA AA EG D07 OQ1 DQ6 Vee VSS VSS Vee 002 DOS 003 D04 Vi A AA AA AA AA PIN NAMES AO - A16 .•••.•••••. .• Address Input E ...................... Chip Enable iN .................... Write Enable G ................... Output Enable DOO - D07 ........ Data Input/Output VCC ....•....... + 5 V Power Supply VSS ......•................ Ground V i - - ......-I G---~-~ MOTOROLA FAST SRAM DATA MCM6726 2-33 1 page WRITE CYCLE 1 (Vii Controlled, See Notes 1 and 2) Symbol MCM6726-10 MCM6726-12 MCM6726-15 Parameter Standard Alternate Min Max Min Max Min Max Unit Notes Write Cycle Time Address Setup Time Address Valid to End of Write Address Valid to End of Write, G High Write Pulse Width Write Pulse Width, G High Data Valid to End of Write Data Hold Time tAVAV tAVWL tAVWH tAVWH twLWH twLEH twLWH twLEH tOVWH twHOX twc tAS tAW tAW twP twP twP twP tow tOH 10 - 12 - 0 - ~, - 9 - f..1JJ' - 8 - 19 ~~ - tv9 - - 8- 9- 5 - (6)V - 0- 0- 15 - ns 3 0 - ns 12 - ns 10 - ns 12 - ns 10 - ns 7 - ns 0 - ns Write Low to Data High-Z Write High to Output Active Write Recovery Time twLOZ twHOX twHAX twz tow twR 05 3- 0- 06 3- 0- 0 7 ns 4,5,6 3 - ns 4,5,6 0 - ns NOTES: 1. A write occurs during the overlap of E low and IN low. 2. For common 1/0 applications, minimization or elimination of bus contention conditions is necessary during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured 200 mV from steady-state voltage with load of Figure 1B. 5. This parameter is sampled and not 100% tested. 6. At any given voltage and temperature, twLOZ max < twHOX min both for a given device and from device to device. A (ADDRESS) E(CHIP ENABLE) Vi (WRITE ENABLE) o(DATA IN) Q(DATAOUT) WRITE CYCLE 1 tAVAV - - - - - - - - - + ( ~-------- ~VWH ---------~--+-tWHAX twLEH twLWH HIGHZ DATA VALID HIGHZ MOTOROLA FAST SRAM DATA MCM6726 2-37 5 Page

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