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PDF MCM6728 Data sheet ( Hoja de datos )
| Número de pieza | MCM6728 | |
| Descripción | 256K x 4 Bit Fast Static Random Access Memory | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MCM6728 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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MOTOROLA
• SEMICONDUCTOR
TECHNICAL DATA
256K X 4 Bit Fast Static Random
Access Memory
The MCM6728 is a 1,048,576 bit static random access memory organized as
262,144 words of 4 bits. This device is fabricated using high performance silicon-gate
SiCMOS technology. Static design eliminates the need for external clocks or timing
strobes.
This device meets JEDEC standards for functionality and revolutionary pinout, and is
available in a 400 mil plastic small-outline J-Ieaded package.
• Single 5 V ± 10% Power Supply
• Fully Static - No Clock or Timing Strobes Necessary
• All Inputs and Outputs Are TTL Compatible
• Three State Outputs
• Fast Access Times: 10, 12, 15 ns
• Center Power and 1/0 Pins for Reduced Noise
BLOCK DIAGRAM
MEMORY
·•• MATRIX
512 ROWS x512 x4
COLUMNS
Vee
Vss
MCM6728
WJ PACKAGE
400 MILSOJ
CASE 810
PIN ASSIGNMENT
AA
A
A
003
Vss
Vee
002
A
A
A
A
•••
w - -.....-i
PIN NAMES
AO - A 17 .. .. .. . .. .... Address Input
E ...................... Chip Enable
W .................... Write Enable
DaO - 003 ........ Data Input/Output
VCC ............ + 5 V Power Supply
VSS ....................... Ground
NC ................. No Connection
MOTOROLA FAST SRAM DATA
MCM6728
2-45
1 page  
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
Symbol
MCM6728-10
MCM6728-12
MCM6728-15
Parameter
Standard Alternate Min Max Min Max Min Max Unit Notes
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Data Valid to End of Write
Data Hold Time
tAVAV
tAVWL
tAVWH
twLWH
twLEH
tOVWH
twHOX
twc
tAS
tAW
twP
twP
tow
tOH
10 -
0-
9-
9-
5-
0-
12 -
0-
10 -
10 -
6-
0-
15 - ns 3
0 - ns
12 - ns
12 - ns
7 - ns
0 - ns
Write Low to Data High-Z
Write High to Output Active
Write Recovery Time
twLQZ
twHQX
twHAX
twz
tow
twR
05
3-
0-
06
3-
0-
0 7 ns 4,5,6
3 - ns 4,5,6
0 - ns
NOTES:
1. A write occurs during the overlap of E low and Wlow.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady-state voltage with load of Figure 1B.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, twLQZ max < twHQX min both for a given device and from device to device.
A (ADDRESS)
E(CHIP ENABLE)
W(WRITE ENABLE)
D(DATA IN)
WRITE CYCLE 1
tAVAV
1 4 - - - - - - - - tAVWH ------~I__..t- twHAX
twLEH
twLWH
tDVWH ----'i4---+--
DATA VALID
a (DATA OUT) _ _---.,;.H;.;.;IG;.;..H;.;;Z~_ _
HIGHZ
MOTOROLA FAST SRAM DATA
MCM6728
2-49
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet MCM6728.PDF ] | |
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