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PDF MCM6729A Data sheet ( Hoja de datos )
| Número de pieza | MCM6729A | |
| Descripción | 256K x 4 Bit Fast Static Random Access Memory | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MCM6729A (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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MOTOROLA
• SEMICONDUCTOR
TECHNICAL DATA
Product Preview
256K x 4 Bit Fast Static Random
Access Memory
The MCM6729A is a 1,048,576 bit static random access memory organized as
262,144 words of 4 bits. This device is fabricated using high performance silicon-gate
BiCMOS technology. Static design eliminates the need for external clocks or timing
strobes.
Output enable (<3) is a special control feature that provides increased system flexi-
bility and eliminates bus contention problems.
This device meets JEDEC standards for functionality and revolutionary pinout, and is
available in a 400 mil plastic small-outline J-Ieaded package.
• Single 5 V ± 10% Power Supply
• Fully Static - No Clock or Timing Strobes Necessary
• All Inputs and Outputs Are TTL Compatible
• Three State Outputs
• Fast Access Times: 8, 10, 12, 15 ns
• Center Power and I/O Pins for Reduced Noise
BLOCK DIAGRAM
MEMORY
MATRIX
5l2ROWSx5l2x4
COLUMNS
Vcc
VSS
MCM6729A
~JPACKAGE E
400 MILSOJ
CASE 857A
PIN ASSIGNMENT
NC A
AA
AA
AA
AA
EG
DOO D03
VCC
VSS
DOl
W
A
A
A
A
NC
VSS
VCC
D02
A
A
A
A
A
NC
PIN NAMES
AO - A17 .............. Address Input
E . . . .. .. . . . . . . . . . . . . . .. Chip Enable
W .................... Write Enable
G ................... Output Enable
DOO - D03 ........ Data InpuVOutput
VCC ............ + 5 V Power Supply
VSS ....................... Ground
NC .................. No Connection
W---4i-1
G----<t-~
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
MOTOROLA FAST SRAM DATA
MCM6729A
2-63
1 page  
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
Symbol
6729A-8
6729A-10 6729A-12 6729A-15
Parameter
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Address Valid to End of Write,
GHigh
Standard Alternate Min Max Min Max Min Max Min Max Unit Notes
tAVAV twc 8 - 10 - 12 - 15 - ns 3
-tAVWL
tAS
0-
0-
0-
0
ns
tAVWH
tAW
8-
9-
10 -
12 -
ns
tAVWH
tAW
7-
8-
9-
10 -
ns
Write Pulse Width
Write Pulse Width, G High
Data Valid to End of Write
Data Hold Time
twLWH
twLEH
twLWH
twLEH
tOVWH
tWHOX
twP
twP
twP
twP
tow
tOH
8-
7-
4-
0-
9-
8-
5-
0-
10 -
9-
6-
0-
12 -
10 -
7-
0-
ns
ns
ns
ns
Write Low to Data High-Z
twLQZ twz 0 4 0 5 0 6 0 7 ns
Write High to Output Active
tWHQX
tow
3-
3-
3-
3-
ns
Write Recovery Time
tWHAX
twR
0-
0-
0-
0-
ns
NOTES:
1. A write occurs during the overlap of E low and Wlow.
2. For common 1/0 applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady-state voltage with load of Figure 1B.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, twLQZ max < tWHQX min both for a given device and from device to device.
4,5,6
4,5,6
A(ADDRESS)
E(CHIP ENABLE)
W(WRITE ENABLE)
D(DATA IN)
Q(DATAOUT)
WRITE CYCLE 1
tAVAV
1 4 - - - - - - - - tAVWH -------ro-~r- tWHAX
~--~---------------
twLEH
twLWH
tDVWH ---.of+-.t-
DATA VALID
HIGHZ
HIGHZ
MOTOROLA FAST SRAM DATA
MCM6729A
2-67
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet MCM6729A.PDF ] | |
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