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Número de pieza | MCM6206BA | |
Descripción | 32K x 8 Bit Fast Static RAM | |
Fabricantes | Motorola Semiconductors | |
Logotipo | ||
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SEMICONDUCTOR TECHNICAL DATA
32K x 8 Bit Fast Static RAM
The MCM6206BA is a 262,144 bit static random access memory organized as
32,768 words of 8 bits. Static design eliminates the need for external clocks or
timing strobes, while CMOS circuitry reduces power consumption and provides
for greater reliability.
This device meets JEDEC standards for functionality and pinout, and is avail-
able in plastic small–outline J–leaded packages.
• Single 5 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• Fast Access Times: 12/15/20/25 ns
• Equal Address and Chip Enable Access Times
• Output Enable (G) Feature for Increased System Flexibility and to
Eliminate Bus Contention Problems
• Low Power Operation: 125 – 140 mA Maximum AC
• Fully TTL Compatible — Three State Output
BLOCK DIAGRAM
A
A
A
A
A
ROW
DECODER
MEMORY MATRIX
A
A
A
A
DQ
INPUT ...
COLUMN I/O
DATA
DQ
CONTROL
COLUMN DECODER
VCC
VSS
E
CIRCUIT
W CONTROL
G
AAAAAA
Order this document
by MCM6206BA/D
MCM6206BA
J PACKAGE
300 MIL SOJ
CASE
810B–03
PIN ASSIGNMENT
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
DQ 11
DQ 12
DQ 13
VSS 14
28 VCC
27 W
26 A
25 A
24 A
23 A
22 G
21 A
20 E
19 DQ
18 DQ
17 DQ
16 DQ
15 DQ
PIN NAMES
A . . . . . . . . . . . . . . . . . . . . Address Input
DQ . . . . . . . . . . Data Input/Data Output
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
VCC . . . . . . . . . . . Power Supply (+ 5 V)
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
REV 1
10/9/96
M© OMoTtoOroRla,OInLc.A19F96AST SRAM
MCM6206BA
1
1 page WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
– 12 – 15 – 20 – 25
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Notes
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Write Pulse Width
tAVAV
12
—
15
—
20
—
25
—
ns
tAVWL
0
—
0
—
0
—
0
— ns
tAVWH 10 — 12 — 15 — 20 — ns
tWLWH, 10 — 12 — 15 — 20 — ns
tWLEH
3
Write Pulse Width,
G High
tWLWH, 10 — 10 — 12 — 15 — ns
tWLEH
4
Data Valid to End of Write
tDVWH
6
—
7
—
8
— 10 — ns
Data Hold Time
tWHDX
0
—
0
—
0
—
0
— ns
Write Low to Output High–Z
tWLQZ — 6 — 7 — 8 — 10 ns 5,6,7
Write High to Output Active
tWHQX
2
—
2
—
2
—
2
— ns 5,6,7
Write Recovery Time
tWHAX
0
—
0
—
0
—
0
— ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. If G goes low coincident with or after W goes low, the output will remain in a high impedance state.
3. All timings are referenced from the last valid address to the first transitioning address.
4. If G ≥ VIH, the output will remain in a high impedance state.
5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device.
6. Transition is measured ±500 mV from steady–state voltage with load of Figure 1b.
7. This parameter is sampled and not 100% tested.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
tAVAV
tAVWH
tAVWL
HIGH Z
tWLQZ
tWLWH
tWLEH
tDVWH
DATA VALID
HIGH Z
tWHAX
tWHDX
tWHQX
MOTOROLA FAST SRAM
MCM6206BA
5
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet MCM6206BA.PDF ] |
Número de pieza | Descripción | Fabricantes |
MCM6206BA | 32K x 8 Bit Fast Static RAM | Motorola Semiconductors |
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