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PDF MCM62V06D Data sheet ( Hoja de datos )

Número de pieza MCM62V06D
Descripción 32K x 8 Bit 3.3 Volt Fast Static RAM
Fabricantes Motorola Semiconductors 
Logotipo Motorola Semiconductors Logotipo



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No Preview Available ! MCM62V06D Hoja de datos, Descripción, Manual

MOTOROLA
• SEMICONDUCTOR
TECHNICAL DATA
Product Preview
32K x 8 Bit 3.3 Volt Fast Static RAM
The MCM62V06D is fabricated using Motorola's high-performance silicon-gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is avail-
able in plastic dual-in-line and plastic small-outline J-Ieaded packages.
• Single 3.3 V ±0.3 V Power Supply
• Fully Static - No Clock or Timing Strobes Necessary
• Fast Access Times: 20, 25, and 35 ns
• Equal Address and Chip Enable Access Times
• Output Enable (<3) Feature for Increased System Flexibility and to Eliminate
Bus Contention Problems
• Low Power Operation: 50 mA Maximum AC
• Fully 3.3 V CMOS - Three State Output
• 100 JlA Standby Mode
A1
A3
A4 -----I
A6-----I
A7-----I
A8-----I
A9-----I
A11-----I
Doa -~P---I
D07--I---f
BLOCK DIAGRAM
MEMORY MATRIX
256 ROWS x
128 x8 COLUMNS
COLUMN 1/0
Vee
Vss
w
MCM62V06D
$MU!2E
300 MIL PLASTIC
CASE 7108
~~JPACK30A0MGILSEOJ
CASE 8108
E
PIN ASSIGNMENT
A14 Vee
A12 W
A7 A13
A6 A8
AS A9
A4 All
A3 IT
A2 Ala
Al E
Aa D07
Doa D06
DOl DOS
D02 D04
Vss D03
PIN NAMES
AO - A14 .. . . . . . . . . . .. Address Input
DOO - D07 ... Data InpuVData Output
W .................... Write Enable
G ................... Output Enable
E ...................... Chip Enable
VCC . '" ..... Power Supply (+ 3.3 V)
VSS ....................... Ground
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
MOTOROLA FAST SRAM DATA
MCM62V06D
3·27

1 page




MCM62V06D pdf
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
Symbol
·20 ·25 ·35
Parameter
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Pulse Width, G High
Data Valid to End of Write
Data Hold Time
Std Alt Min Max Min Max Min Max Unit Notes
tAVAV twc 20 - 25 - 35 - ns 3
-tAVWL
tAS
0
0-
0-
ns
-tAVWH
tAW
15 -
20 -
30
ns
twLWH,
twP
15 -
20 -
30 -
ns
twLEH
twLWH,
twLEH
tDVWH
twP
tow
12 -
8-
15 -
10 -
20 -
12 -
ns
ns
4
twHDX
tDH
0-
0-
0-
ns
Write Low to Output High-Z
twLQZ twz 0 8 0 10 0 11 ns
Write High to Output Active
twHQX
tow
4-
4-
4-
ns
Write Recovery Time
twHAX
tWR
0-
0-
0-
ns
NOTES:
1. A write occurs during the overlap of E low and Wlow.
2. If G goes low coincident with or after Wgoes low, the output will remain in a high impedance state.
3. All timings are referenced from the last valid address to the first transitioning address.
4. If G ~ VIH, the output will remain in a high impedance state.
5. At any given voltage and temperature, twLQZ max is less than twHQX min, both for a given device and from device to device.
6. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
5,6,7
5,6,7
A(ADDRESS)
E(CHIP ENABLE)
W(WRITE ENABLE)
o(DATA IN)
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
tAVAV -----------i~
1 4 - - - - - - - - IAVWH - - - - - -........--101- twHAX
twLWH
twLEH
IDVWH - ___014-....-
DATA VALID
Q(DATAOUn
HIGHZ
HIGHZ
MOTOROLA FAST SRAM DATA
MCM62V06D
3-31

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