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PDF MCM6226B Data sheet ( Hoja de datos )
| Número de pieza | MCM6226B | |
| Descripción | 128K x 8 Bit Static Random Access Memory | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
• SEMICONDUCTOR
TECHNICAL DATA
Product Preview
128K x 8 Bit Static Random
Access Memory
The MCM62268 is a 1,048,576 bit static random access memory organized as
131,072 words of 8 bits, fabricated using high-performance silicon-gate CMOS
technology. Static design eliminates the need for external clocks or timing strobes while
CMOS circuitry reduces power consumption and provides for greater reliability.
The MCM62268 is equipped with both chip enable (8 and E2) and output enable (G)
pins, allowing for greater system flexibility and eliminating bus contention problems.
The MCM62268 is available in 300 mil and 400 mil, 32 lead surface-mount SOJ
packages.
• Single 5 V ± 10% Power Supply
• Fast Access Times: 15/17/20/25/35 ns
• Equal Address and Chip Enable Access Times
• All Inputs and Outputs are TTL Compatible
• Three State Outputs
• Low Power Operation: 130/125/120/115/110 mA Maximum, Active AC
BLOCK DIAGRAM
A3
A4
A7
A6--,~---.
•AS
ROW •
DECODER •
Al0
A9
A8
Al
MEMORY MATRIX
S12ROWSx
2048 COLUMNS
COLUMN I/O
COLUMN DECODER
WG=:::::!:::::d
A2 A13A12 All AO A16 A1S A14
MCM6226B
WJ PACKAGE
400 MILSOJ
CASE 857A
, JPACKAGE
300 MILSOJ
CASE 857
PIN ASSIGNMENT
NC VCC
AO A16
AI E2
A2 W
A3 A1S
A4 AI4
AS A13
A6 AI2
A7 G
AS All
A9 Ef
Al0 D07
DOO D06
DOl DOS
D02 D04
VSS D03
PIN NAMES
AD - A 16 ............. Address Inputs
W ..................... Write Enable
G ................... Output Enable
8, E2 ................ Chip Enables
DOD - DO? . . . . .. Data Inputs/Outputs
NC .................. No Connection
VCC ............. + 5 V Power Supply
VSS ........................ Ground
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
MOTOROLA FAST SRAM DATA
MCM62268
3-51
1 page  
WRITE CYCLE 1 (W Controlled, See Notes 1, 2, 3, and 4)
Symbol
62268-15 62268-17 62268-20 62268-25 62268-35
Parameter
Std Alt Min Max Min Max Min Max Min Max Min Max Unit Notes
Write Cycle Time
Address Setup Time
Address Valid to End of
Write
- - --tAVAV
twc
15
17
20
25
35 -
ns
tAVWL
tAS
-0 - 0 - 0 - 0
0-
ns
tAVWH tAW 12 - 14 - 15 - 17 - 20 - ns
5
Write Pulse Width
-twLWH twP 12 - 14 - 15
17 -
20 -
ns
Data Valid to End of Write tDVWH
tow
7-
8-
--8 - 10
11 -
ns
Data Hold Time
twHDX
tDH
-0 - 0 - 0 - 0
0-
ns
Write Low to Data High-Z
Write High to Output Active
Write Recovery Time
tWLOZ
twHQX
twHAX
twz
tow
twR
06
5-
0-
07
5-
0-
07
5-
0-
08
5-
0-
0 B ns 6,7,8
5-
ns 6,7,8
-0 ns
NOTES:
1. A write occurs during the overlap of E low and Wlow.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well ~s minimization or elimination of bus con-
tention conditions during read and write cycles.
E1'and3. E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.
4. If G goes low coincident with or after Wg~es low, the output will remain in a high-impedance state.
.
5. All timings are referenced from the last valid address to the first transitioning address.
6. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8. At any given voltage and temperature, twLQZ max is less than twHQX min both for a given device and from device to device.
WRITE CYCLE 1 (W Controlled See Notes 1, 2, 3, and 4)
A(ADDRESS)
E(CHIP ENABLE)
j - . - - - - - - - - - - tAVAV ---------~
~---------~VWH --------------~.-~~~AA
iN (WRITE ENABLE)
tWLWH
twLEH
~--- tDVWH ----+ir----.....
D(DATA IN)
DATA VALID
~~zj
I- 'r-:~
a(DATA OUT) -----.;.H~IGH.;..;;;..Z-~<XXXZ)I-·--_H;.;;..;;'G;.;.;...;;H.Z~--_KXXXX>-
MOTOROLA FAST SRAM DATA
MCM6226B
3-55
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MCM6226B.PDF ] | |
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