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PDF MCM6287B Data sheet ( Hoja de datos )
| Número de pieza | MCM6287B | |
| Descripción | 64K x 1 Bit Fast Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MCM6287B (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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MOTOROLA
• SEMICONDUCTOR
TECHNICAL DATA
64K X 1 Bit Fast Static RAM
The MCM6287B is fabricated using Motorola's high-performance silicon-gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for greater
reliability.
This device meets JEDEC standards for functionality and pinout, and is available
in plastic dual-in-line and plastic small-outline J-Ieaded packages.
• Single 5 V ± 10% Power Supply
• Fully Static - No Clock or Timing Strobes Necessary
• Fast Access Times: 12, 15, 20, 25, and 35 ns
• Equal Address and Chip Enable Access Times
• Low Power Operation: 110 - 150 mA Maximum AC
• Fully TTL-Compatible - Three-State Output
• Separate Data Input and Output
BLOCK DIAGRAM
A3
A4
A5
A6
ROW
DECODER
A13
A14
A15
MEMORY MATRIX
12SROWSx
512 x 1COLUMNS
Da
W_.--,._-,
PIN NAMES
AO - A15 ................ Address Input
E ........................ Chip Enable
W ....................... Write Enable
a ........................ Data Output
VCC .............. + 5 V Power Supply
VSS ......................... Ground
D .......................... Data Input NC ................... No Connection
MCM6287B
~--
1 PPACKAGE
300 MIL PLASTIC
CASE 736A
24~'JPACKAGE
1 300 MIL SOJ
CASE 810A
PIN ASSIGNMENTS
DUAL-IN-L1NE
VCC
A15
A14
A13
A12
All
Al0
A9
AS
D
E
SOJ
AO VCC
A15
A14
A13
A4 A12
A5 NC
All
A10
A9
a AS
WD
VSS '---_ _--' E
MCM6287B
3-108
MOTOROLA FAST SRAM DATA
1 page  
WRITE CYCLE 1 (iiJ Controlled, See Notes 1, 2, and 3)
Symbol
·12 ·15 ·20 ·25 ·35
Parameter
Std Alt Min Max Min Max Min Max Min Max Min Max Unit Notes
Write Cycle Time
-tAVAV twc
12 -
15
20 - 25 - 35 - ns 2
Address Setup Time
tAVWL tAS
0-
0-
0-
0-
0 - ns
-Address Valid to End of Write tAVWH tAW 10
12 -
15 -
20 -
25 -
ns
Write Pulse Width
twLWH, twP
10 -
12 -
15 -
20 -
25 -
ns
twLEH
Data Valid to End of Write
tOVWH tow
6-
7-
8 - 10 -
15 - ns
Data Hold Time
twHOX tOH
0-
0-
0-
0-
0 - ns
Write Low to Output High-Z
twLQZ twz 0 6 0 7 0 8 0 10 0 15 ns 3,4,5
Write High to Output Active
twHQX tow
4-
4-
4-
4-
-4 ns 3,4,5
- -Write Recovery Time
twHAX twR
0
NOTES:
I 1. A write occurs during the overlap of E low and Vi low.
-
0
0-
0
0-
ns 3,4,5
2. All timings are referenced from the last valid address to the first transitioning address.
3. At any given voltage and temperature, twLQZ max < twHQX min, both for a given device and from device to device.
4. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
5. This parameter is sampled and not 100% tested.
WRITE CYCLE 1 (See Note 2)
~-------------------~VAV ------------------~
A(ADDRESS)
1 4 - - - - - - - - - tAVWH -----------~.......+-twHAX
E(CHIP ENABLE)
W(WRITE ENABLE)
twLWH,
twLEH
1..---- tDVWH -----+j._--__il*""
o(DATA IN)
DATA VALID
~~~j Ia (DATA OUT) _ _H_IGH_.Z_~<XXXXZ)>>--_ _......;H.;;.;;.IGH;..;..;;.Z_ _I..-.-tWH-Q-X-lJXXXX>--
MCM6287B
3-112
MOTOROLA FAST SRAM DATA
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MCM6287B.PDF ] | |
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