PDF MCM56824AZP Data sheet ( Hoja de datos )

Número de pieza	MCM56824AZP
Descripción	8K x 24 Bit Fast Static RAM
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA • SEMICONDUCTOR TECHNICAL DATA Product Preview DSPRAMTM 8K X 24 Bit Fast Static RAM The MCM56824AZP is a 196,608 bit static random access memory organized as 8,192 words of 24 bits, fabricated using Motorola's high-performance silicon-gate CMOS technology. The device integrates an 8K x 24 SRAM core with multiple chip enable inputs, output enable, and an externally controlled single address pin multi- plexer. These functions allow for direct connection to the Motorola DSP56001 Digital Signal Processor and provide a very efficient means for implementation of a re- duced parts count system requiring no additional interface logic. The availability of multiple chip enable (Ef and E2) and output enable (<3) inputs provides for greater system flexibility when multiple devices are used. With either chip enable input unasserted, the device will enter standby mode, useful in low- power applications. A single on-chip multiplexer selects A12 or XIY as the highest order address input depending upon the state of the Vis control input. This feature allows one physical static RAM component to efficiently store program and vector or scalar operands by dynamically re-partitioning the RAM array. Typical applications will logically map vector operands into upper memory with scalar operands being stored in lower memory. By connecting DSP56001 address A15 to the VECTORI SCALAR (ViS) MUX control pin, such partitioning can occur with no additional com- ponents. This allows efficient utilization of the RAM resource irrespective of operand type. See application diagrams at the end of this document for additional information. Multiple power and ground pins have been utilized to minimize effects induced by output noise. The MCM56824AZP is available in a 9 x 10 grid, 86 bump surface mount OMPAC. • Single 5 V ± 10% Power Supply • Fast Access and Cycle Times: 20/25/35 ns Max • Fully Static Read and Write Operations • Equal Address and Chip Enable Access Times • Single Bit On-Chip Address Multiplexer • Active High and Active Low Chip Enable Inputs • Output Enable Controlled Three State Outputs • High Board Density PLCC Package • Low Power Standby Mode • Fully TTL Compatible MCM56824AZP 9 x 10 GRID 86 BUMP OMPAC CASE 896A-01 PIN NAMES AO - A11 ............... Address Inputs A12, XJY .......... Multiplexed Address vis ... ...... Address Multiplexer Control Vi ....................... Write Enable n, E2 ................... Chip Enable G ...................... Output Enable DOO - 0023 .......... Data Input/Output VCC ............... +5 V Power Supply VSS .......................... Ground NC .................... No Connection For proper operation of the device, all VSS pins must be connected to ground. DSPRAM is a trademark of Motorola, Inc. This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. MCM56824AZP 4-10 MOTOROLA FAST SRAM DATA 1 page AC OPERATING CONDITIONS AND CHARACTERISTICS (Vee = 5.0 V ± 10%, TA = 0 to + 70oe, Unless Otherwise Noted) Input Timing Measurement Reference Level. . . . . . . . . . . . . .. 1.5 V Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 to 3.0 V Input Rise/Fall Time .................................... 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . .. 1.5 V Output Load ............ See Figure 1A Unless Otherwise Noted READ CYCLE TIMING (See Notes 1,2, and 3) Symbol MCM56824AZP-20 MCM56824AZP-25 MCM56824AZP-35 Parameter Stndard Alternate Min Max Min Max Min Max Unit Notes Read Cycle Time -tAVAV tRC 20 25 - 35 - ns Address Access Time tAVOV tAA - 20 - 25 - 35 ns MUX Control Valid to Output Valid tvSVOV tAA - 20 - 25 - 35 ns Chip Enable to Output Valid tE1LOV tE2HOV tAC1 tAC2 - 20 - 25 - 35 ns 4 Output Enable to Output Valid tGLOV tOE - 8- 10 - 15 ns Output Active from Chip Enable tE1LOX tCLZ 2 - 2- 0 - ns 4,5 tE2HOX Output Active from Output Enable tGLOX toLZ 0 - 0- 0 - ns 5 Output Hold from Address Change Output Hold from MUX Control Change tAXOX tvSXOX tOH tvSOH 4 4 - - 5- 5- 5 - ns 5 - ns Chip Enable to Output High Z tE1HOZ tCHZ 0 10 0 15 0 15 ns 4,5 tE2LOZ Output Enable High to Output tGHOZ toHZ 0 8 0 15 0 15 ns 5 HighZ NOTES: 1. A read cycle is defined by Whigh. 2. All read cycle timings are referenced from the last valid address or vector/scalar transition to the first address or vector/scalar transition. 3. Addresses valid prior to or coincident with ET going low or E2 going high. 4. ET in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high. S. Transition is measured ±500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tE1 HOZ max is less than tE1 LOX min, tE2LOZ max is less than tE2HOX min, and tGHOZ max is less than tGLOX min for a given device and from device to device. READ CYCLE A (ADDRESS) =~~t---------------------I-AAQ~X~~=~-I--vis(MUXCONTROL) IAVAV -IIAVQV - - - --- tvSVQV - - - -.1 = - - [ - - - - : - - - E1 (CHIP ENABLE) IE1LQV IE1HQZ G(OUTPUT ENABLE) Q(DATAOUT) HIGH·Z 1 - - . - - - - IGHQZ - - - - - . l DATA VALID MCM56824AZP 4-14 MOTOROLA FAST SRAM DATA 5 Page

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