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PDF MCM62X308 Data sheet ( Hoja de datos )
| Número de pieza | MCM62X308 | |
| Descripción | 8K x 8 Bit Fast Static Dual Ported Memory | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
Product Preview
Synchronous Line Buffer:
8K X 8 Bit Fast Static Dual
Ported Memory
With IEEE Standard 1149.1 Test Access
Port and Boundary-Scan (JTAG)
MCM62X308
"'JPACKAGE
1 300 MIL SOJ
CASE 810B
The MCM62X308 is a synchronous, dual ported memory organized as 8,192
words of 8 bits each, fabricated using Motorola's double-metal, double-poly, 0.65 11m
CMOS process. It is intended for high speed video or other applications which pro-
cess data on a line-by-line basis. Through the use of a single clock and port control
inputs, separate read and write data ports provide simultaneous access to a com-
mon memory array. Simultaneous read/write access to the same address location
is also allowed, with old data being read followed by a write of the new data. This
allows multiple devices to be cascaded with the output of one directly driving the
input of another. In this configuration the data stream can be tapped at strategic in-
terconnect points to perform various digital filtering functions.
Since there are no external address inputs, separate internal Read and Write
Address Counters are provided as a means of indexing the memory array. These
counters are preloaded and then selectively incremented or decremented by assert-
ing Read Enable (RE) and Write Enable(WE) inputs, allowing cycle to cycle control.
The address counters can be reloaded back to their initial values through the use
of the Read Reload (RR) and Write Reload (WR) control inputs. These inputs initiate
the transfer of Address Reload Register values into the Address Counters which in-
dex the memory array. When an address counter reaches 0000 (on down count) or
FFFF (on up count), it will roll over on the next count. The TDI input is used to write
the Reload Registers using special Test Access Port instructions.
The Address Counters are 16 bits long, and only 13 of the 16 bits are required to
index the 8K deep memory array. The remaining three bits are used for depth expan-
sion. These three bits are compared to the lower three bits in the control register and
as long as they are equal that port will remain active. If the bits do not compare the
port will become inactive, however the counter will continue to count on the rising
edge of K as long as the port enable signal (RE or WE) is asserted. The TDI input
is used to write the Control Register using special Test Access Port instructions.
The Output Enable Input can be programmed to be either synchronous or asynch-
ronous through the Control Register.
The MCM62X308 is available in a 28 pin SOJ package.
• 8K x 8 Fast Access Static Memory Array
• Single 5 V Power Supply -MCM62X308-15-5: ± 5%
MCM62X308-17: ± 10%
• Synchronous, Simultaneous ReadlWrite Memory Access
• 50 MHz Maximum Clock Cycle Time, < 15 ns Read Access
• Single Clock Operation
• Separate ReadlWrite Address Counters with Reload Control
• Separate Up/Down Counter Control for Both Read and Write
• Programmable Output Enable Control (Synchronous or Asynchronous)
• Cascadable I/O Interface
• IEEE Standard 1149.1 Test Port (JTAG)
• Expand 10 Register for Depth Expansion
• High Board Density SOJ Package
• Fully TTL Compatible
PIN ASSIGNMENT
07 07
06 06
05 05
04 04
03 03
02 02
01 01
00 00
VOO VSS
K IT
WE RE
WR RR
TOI TOO
TCK TMS
PIN NAMES
K .. .. .. .. . .. . . .. .. .. .. .. . .. ... Clock Input
WE ..................... Write Enable Input
WR ............. Write Address Reload Input
RE .....................Read Enable Input
RR ............. Read Address Reload Input
G .................... Output Enable Input
DO - D7 ....................... Data Inputs
00 - 07 . . . . . . . . . . . . . . . . . . . .. Data Outputs
TCK ...................... Test Clock Input
TMS ..................... Test Mode Select
TDI ........................ Test Data Input
TDO . . . . . . . . . . . . . . . . . . . .. Test Data Output
VDD ................... + 5 V Power Supply
VSS ............................. Ground
ThiS document contains information on a new product unCler development. Motorola reserves the right to change or discontinue this product wltnout notice.
MCM62X308
4·28
MOTOROLA FAST SRAM DATA
1 page  
READIWRITE CYCLE TIMING DIAGRAM
NOTE: THIS TIMING DIAGRAM ALSO SHOWS THE FUNCTIONALITY OF THE PART
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MCM62X308
4-32
MOTOROLA FAST SRAM DATA
5 Page 
DEVICE SPECIFIC (PUBLIC) INSTRUCTIONS
LDCONT INSTRUCTION
The Control Register is an eight bit register that contains the
control bits for the Address Registers and Counters and the
Output Enable pin. When the LDCONT TAP instruction is
loaded into the Instruction Register, the Control Register is
placed between TDI and TDO when the TAP controller is in the
Shift-DR state (Table 10). The power-up/preload state and
function of the Control bits are found in Table 3.
The Expand ID bits provide system depth expansion. These
three bits are compared to the upper three bits in the address
counters. As long as the three Expand-ID bits match the three
upper bits in the address counters the port will stay active. If
they do not match, the port will deactivate (Le., outputs will
High-Z or write will be disabled); however, the counters will
continue counting as long as RE and WE remain asserted
(Le., high) at the rising edge of Clock.
The Reload Control bits (3 and 5) are used to control either
reloading the Read and Write Address Counters from the
Reload Registers or clearing the counter when RR or WR is
asserted. If these bits are set low the counters they control will
be cleared to all zeroes if the appropriate reload signal (RR or
WR) is asserted and any value in the Reload Register is ig-
nored. This means that if the initial address value desired is
address 0000 (or FFFF when counting down) then there is no
need to load the Address Reload Registers using the
LDRREG, LDWREG, or the LDBREG instructions in the fol-
lowing description. If these bits are set high the counters are
loaded up with the values in the Reload Registers when the
appropriate reload signal (RR or WR) is asserted.
The Up/Down count bits (4 and 6) determine the direction
in which the respective Address Counter will count; if the bit
is set low the counter will count up and if set high the counter
will count down. If the counters are set to count down and the
Reload control is set to the clear counter mode, then the initial
value in the counters will be FFFF. To ensure that the counter
will function properly, a reload (using RR or WR) is required
after the count direction is switched.
The Output Enable control bit (7) determines the function-
ality of the Output Enable pin, G. When the bit is low, G func-
tions asynchronously. When set high, G functions synchro-
nously and must meet the specified setup and hold times to
the Clock K.
The Control Register will also be preloaded. When the
instruction 0010 (LDCONT) is in the Instruction Register and
the controller is in the Capture-DR state the above preload
values (all zeroes) will be loaded into the Control Register. All
zeroes will also be loaded in the Control Register at power-up.
While new values are shifted in from TDI in the Shift-DR
state, all zeroes will be output on TDO for the first eight bits.
LOR REG, LDWREG, AND LDBREG TAP INSTRUCTIONS
There are three instructions that may be used to load the 16
bit address reload registers: LDRREG (Load Read Address
Reload Register), LDWREG (Load Write Address Reload
Register), and LDBREG (Load both Address Reload Regis-
ters, Write followed by Read). Figure 3 illustrates how the Re-
load registers are placed between TDI and TDO. Tables 7, 8,
and 9 describe each register. These instructions would be
used only if the user needed to load the Reload Registers with
a non-zero value. If the Address Counters are to always be re-
set to zeroes (or all1s if counting down) then only the Control
Register need be loaded to affect a reset of the counters.
The TAP controller has been set up to make it easier for the
user to serially load the Reload Registers. When the TAP con-
troller is clocked into the Capture-IR state (see state diagram)
the instruction for loading both registers (0101) will be pre-
loaded into the shift register. This allows the user to go directly
to the Update-I R instead of having to serially shift this instruc-
tion in through the TDI port. Once the load instruction has been
entered the user can then clock over to the Capture-DR state
where the value for the reload register(s) is serially loaded
(see Figure 3).
RDCOUNT TAP INSTRUCTION
The RDCOUNT scan register is accessible after the
RDCOUNT instruction is loaded into the TAP instruction regis-
ter in the Shift-IR state and the TAP controller is then moved
to the Shift-DR state. This scan register can then be used to
shift out the values of the Read and Write Address Counters
The RDCOUNT scan-register is a sample only register and
can not be used to load values into the counters. See Table 4.
EZWRITE TAP INSTRUCTION AND SCAN PATH
The EZWRITE TAP instruction is provided to allow the user
to more easily and quickly write a large number of bytes to the
device serially through the TDI port. EZWRITE shortens the
scan path for a serial write to just the 8 bit Data in register (see
Table 5).
The most likely use of this instruction is as follows: the user
would first load the Control Register using the LDCONT
instruction. This would initialize the Expand ID bits and the
Write Counter. The Write Reload Register will need to be
Bit
No.
0-2
3
4
5
6
7
Power Up and
Preload State
000
0
0
0
0
0
Table 3 Control Register Bit Description
Function
Expand ID bits for comparison with the upper 3 bits of the Read and Write Address counters
Reload Control of Write Address Counter (0 =clear counter, 1 =reload)
UplDown count bit for Write Address Counter (0 =count up, 1 =count down)
Reload Control of Read Address Counter (0 =clear counter, 1 =reload)
Up/Down count bit for Read Address Counter (0 =count up, 1 =count down)
G Control (0 =asynchronous, 1 =synchronous)
MCM62X308
4-38
MOTOROLA FAST SRAM DATA
11 Page | ||
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| PDF Descargar | [ Datasheet MCM62X308.PDF ] | |
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