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PDF MCM62486A Data sheet ( Hoja de datos )
| Número de pieza | MCM62486A | |
| Descripción | Synchronous Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
• SEMICONDUCTOR
TECHNICAL DATA
32K X 9 Bit BurstRAMTM
Synchronous Static RAM
With Burst Counter and Self-Timed Write
MCM62486A
The MCM62486A is a 294,912 bit synchronous static random access memory
designed to provide a burstable, high-performance, secondary cache for the i486
and Pentium™ microprocessors. It is organized as 32,768 words of 9 bits, fabricated
with Motorola's high-performance silicon-gate CMOS technology. The device inte-
grates input registers, a 2-bit counter, high speed SRAM, and high drive capability
outputs onto a single monolithic circuit for reduced parts count implementation of
cache data RAM applications. Synchronous design allows precise cycle control with
the use of an external clock (K). CMOS circuitry reduces the overall power con-
sumption of the integrated functions for greater reliability.
Addresses (AO - A14), data inputs (DO - D8), and all control signals except
output enable (<3) are clock (K) controlled through positive-edge-triggered
noninverting registers.
Bursts can be initiated with either address status processor (ADSP) or address
status cache controller (ADSC) input pins. Subsequent burst addresses can be
generated internally by the MCM62486A (burst sequence imitates that of the
i486 and Pentium) and controlled by the burst address advance (ADV) input pin.
The following pages provide more detailed information on burst controls.
Write cycles are internally self-timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off-chip write pulse generation
and provides increased flexibility for incoming signals.
The MCM62486A will be available in a 44-pin plastic leaded chip carrier
(PLCC). Multiple power and ground pins have been utilized to minimize effects
induced by output noise. Separate power and ground pins have been employed
for DOO - D08 to allow user-controlled output levels of 5 volts or 3.3 volts.
A2
A3
A4
A5
A6
VSS
DOO
DOl
VSSO
VCCO
D02
FN PACKAGE
44-LEAD PLCC
CASE 777
PIN ASSIGNMENT
1~lfu.<C..<-C0I<>C0<0C0<C:><::0U> ,.<.C..<.Ccom<C 0<...C...
5 4 3 2 1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
16 30
1718 19 20 21 2223 24 2526 272r
8 g ~ 1:1: 8 ~ l<!l g Ie;; ~ g
o en»>
oen
>>
All
EA12
A13
A14
VSS
D07
D06
VSSO
VCCO
DOS
D04
• Single 5 V ± 10% Power Supply
• Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level Compatibility
• Fast Access Times: 11/12/14/19/24 ns Max and Cycle Times: 15/20/25/30 ns Min
• Internal Input Registers (Address, Data, Control)
• Internally Self-Timed Write Cycle
• ADSP, ADSC, and ADV Burst Control Pins
• Asynchronous Output Enable Controlled Three-State Outputs
• Common Data Inputs and Data Outputs
• High Output Drive Capability: 85 pF per I/O
• High Board Density PLCC Package
• Fully TTL-Compatible
• Active High and Low Chip Select Inputs for Easy Depth Expansion
PIN NAMES
AO - A14 ............. Address Inputs
K ............................ Clock
IN ..................... Write Enable
G ................... Output Enable
SO, Sf ................. Chip Selects
ADV . . . . . . . .. Burst Address Advance
ADSP, ADSC ......... Address Status
Dao - Da8 . . . . . . .. Data InpuVOutput
VCC ............. + 5 V Power Supply
Vcca .... Output Buffer Power Supply
VSS ....................... Ground
Vssa ......... Output Buffer Ground
All power supply and ground pins must
be connected for proper operation of
the device. VCC ~ Vcca at all times
including power up.
BurstRAM is a trademark of Motorola. Inc.
i486 and Pentium are trademarks of Intel Corp.
MOTOROLA FAST SRAM DATA
MCM62486A
4-67
1 page  
AC OPERATING CONDITIONS AND CHARACTERISTICS
= =(VCC, VCCQ 5.0 V ± 5%, TA 0 to + 70°C, for device MCM62486A-11)
= = =(VCC 5.0 V ± 10%, VCCQ 5.0 V or 3.3 V ± 10%, TA 0 to + 70°C, for all other devices)
Input Timing Measurement Reference level. . . . . . . . . . . . . .. 1.5 V
Input Pulse levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 to 3.0 V
Input Rise/Fall Time .................................... 3 ns
Output Timing Reference level . . . . . . . . . . . . . . . . . . . . . . . . .. 1.5 V
Output load ................ Figure 1A Unless Otherwise Noted
READIWRITE CYCLE TIMING (See Notes 1, 2, and 3)
Symbol
62486A-11 62486A-12 62486A-14 62486A-19 62486A-24
Parameter
Std Alt Min Max Min Max Min Max Min Max Min Max Unit Notes
Cycle Time
tKHKH
tCYC 15 -
20 -
20 -
25 -
30 -
ns
Clock Access Time
tKHOV
tCD -
11 - 12 - 14 -
19 - 24 ns
4
Output Enable Access
tGlOV
tOE -
5-
5-
6-
7-
7 ns
Clock High to Output Active tKHOX1
tDC1
6-
6-
6-
6-
6-
ns
Clock High to 0 Change
-tKHOX2 tDC2
3
3-
4-
4-
4-
ns
Output Enable to 0 Active
tGlOX
toLZ 0 -
0-
0-
0-
0-
ns
Output Disable to 0 High-Z
Clock High to 0 High-Z
tGHOZ
tKHOZ
toHZ
tcz
-
-
6-
6-
6-
6-
6-
6-
7-
6-
7 ns
6 ns
5
Clock High Pulse Width
tKHKl
tCH 5.5 -
7-
8-
6-
6-
ns
Clock low Pulse Width
tKlKH
tCl 5.5 -
7-
8-
6-
6-
ns
Setup Times: Address tAVKH tAS 2 - 2 - 3 - 3 - 3 - ns 6
Address Status tADSVKH
Data In tDVKH
tss
tDS
Write
Address Advance
Chip Select
twVKH
tADVVKH
tSOVKH
tws
tS1VKH
Hold Times:
-Address tKHAX tAH 2 2 - 2 - 2 - 2 - ns 6
Address Status tKHADSX tSH
Data In tKHDX
tDH
Write tKHWX
Address Advance tKHADVX
twH
Chip Select tKHSOX
tKHS1X
NOTES:
1. A read cycle is defined by Whigh or ADSP low for the setup and hold times. A write cycle is defined by Wlow and ADSP high for the setup
and hold times.
2. All read and write cycle timings are referenced from K or G.
3. G is a don't care when Wis sampled low.
4. The MCM62486A-19 and MCM62486A-24 will meet all 33 MHz specifications, even when K is running at 66 MHz.
5. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tKHOZ max is less than tKHOX1 min for a given device and from device to device.
6. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of clock (K) whenever ADSP
and ADSC are low and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges
of K when the chip is selected.Chip select must be true (S1 low and SO high) at each rising edge of clock for the device (when ADSP or ADSC
is low) to remain enabled. Timings for S1 and SO are similar.
IOUTPUT
AC TEST LOADS
f ifZo=50n ::-
50n
5V
:dOUTPUT
255 n
+ 480n
5 pF
(INCLUDING
SCOPE AND JIG)
Figure 1A
Figure 18
NOTE: For information on output I-V characteristics, see Chapter 8, Section 1.
MOTOROLA FAST SRAM DATA
MCM62486A
4-71
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MCM62486A.PDF ] | |
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