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PDF MCM62981 Data sheet ( Hoja de datos )
| Número de pieza | MCM62981 | |
| Descripción | 64K x 4 Bit Fast Synchronous ParityRAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MCM62981 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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MOTOROLA
• SEMICONDUCTOR
TECHNICAL DATA
64K X 4 Bit Fast Synchronous
ParityRAMTM
The MCM62981 is a 262,144 bit synchronous static random access memory
organized as 65,536 words of 4 bits, fabricated using Motorola's high-performance
silicon-gate CMOS technology. The device integrates a 64K x 4 SRAM core with
advanced peripheral circuitry consisting of positive edge triggered registers on
address and synchronous write enable inputs. Asynchronous controls include
asynchronous write strobes and output enable (G).This device has increased output
drive capability supported by multiple power pins. Four asynchronous write strobes
(AWO - AW3) are provided to allow each bit position to be written individually, there-
by simplifying the task of supporting byte parity. This x4 organized SRAM is ideally
suited for parity on 32-bit words.The device is functionally similar to the MCM62980
and MCM62990 with the only difference being the individual bit write capablilty.
Write cycles are differentiated from read cycles by the state of the synchronous
write enable pin (SW) at the rising edge of clock (K). Write cycles are completed
only if the appropriate asynchronous write strobe (AWx) is asserted within the speci-
fied setup time of the following rising edge of clock (K). Write cycles may be aborted
by ensuring that each AWx is negated by the time the clock transitions to the low
state.
Additional power supply pins have been utilized and placed on the package for
maximum performance. In addition, one set of power pins is electrically isolated
from the other set and supplies power only to the output buffers. This allows con-
necting the output buffers to 3.3 V instead of 5.0 V if desired. If 3.3 V output levels
are chosen, the output buffer impedance in the "high" state is approximately equal
to the impedance in the "low" state which allows simple yet effective transmission
line terminations to be achieved.
The MCM62981 will be available in a 32-pin 300 mil plastic SOJ.
Applications for this device include parity RAMs for fast data caches.
• Single 5 V ± 10% Power Supply
• Choice of 5.0 V or 3.3 V ± 10% Power Supplies for Output Buffers
• Fast Access and Cycle Times: 15/20 ns Max
• Fully Synchronous Operation, Single Clock Control
• Clock Timed Writes with Asynchronous Late Write Abort
• Each Bit Position Individually Writeable for Simple Parity Support
• Registered Address Inputs
• Common Data Inputs and Data Outputs
Output Enable Controlled Three-State Outputs
• High Output Drive Capability: 85 pF/Output at Rated Access Time
MCM62981
J PACKAGE
300 MILSOJ
CASE 857
PIN ASSIGNMENT
K Vee
AO A1S
Al A14
P:l. A13
A3 A12
A4 All
AS Al0
A6 Veco
A7 VSSO
AS DOO
A9 DOl
SW D02
G D03
VSS AW3
Ne AW2
AWO AWl
II
PIN NAMES
AO - A15 .. . . . . . . . . . . . .. Address Inputs
AWO - AW3 . Asynchronous Write Strobes
SW . . . . . . . . .. Synchronous Write Enable
K ............................... Clock
G ...................... Output Enable
Daa - Da3 . . . . . . . . . .. Data InpuVOutput
VCC .. .. .. .. .. .. ... + 5 V Power Supply
Vcca ...... Output Buffer Power Supply
Vssa ............ Output Buffer Ground
VSS .......................... Ground
NC ....................... No Connect
All power supply and ground pins must be
connected for proper operation of the device.
VCC ~ Vcca at all times including power up.
ParityRAM is a trademark of Motorola Inc.
MOTOROLA FAST SRAM DATA
MCM62981
4-117
1 page  
READ CYCLES
J4----tKHKH - - - - . t
K
ADDRESS
DATA OUT
K
ADDRESS
READ - WRITE - READ CYCLES
DATAIN _ _-+-_ _ _ _ _-+_ _--(
DATA OUT
READ
WRITE
READ
ABORTED WRITE
I
MOTOROLA FAST SRAM DATA
MCM62981
4-121
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet MCM62981.PDF ] | |
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