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PDF MCM67B618 Data sheet ( Hoja de datos )
| Número de pieza | MCM67B618 | |
| Descripción | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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I
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
MCM67B618
Product Preview
64K x 18 Bit BurstRAMTM
Synchronous Fast Static RAM
With Burst Counter and Self-Timed Write
The MCM67B618 is a 1,179,648 bit synchronous fast static random access memory
designed to provide a burstable, high-performance, secondary cache for the i486 and
Pentium™ microprocessors. It is organized as 65,536 words of 18 bits, fabricated with
Motorola's high-performance silicon-gate BiCMOS technology. The device integrates
input registers, a 2-bit counter, high speed SRAM, and high drive capability outputs onto
a single monolithic circuit for reduced parts count implementation of cache data RAM
applications. Synchronous design allows precise cycle control with the use of an
external clock (K). BiCMOS circuitry reduces the overall power consumption of the
integrated functions for greater reliability.
Addresses (AD - A15), data inputs (DO - D17), and all control signals except
output enable (G) are clock (K) controlled through positive-edge-triggered
noninverting registers.
009
Bursts can be initiated with either address status processor (ADSP) or
address status cache controller (ADSC) input pins. Subsequent burst
addresses can be generated internally by the MCM67B618 (burst sequence
imitates that of the i486 and Pentium) and controlled by the burst address
advance (ADV) input pin. The following pages provide more detailed infor-
mation on burst controls.
Write cycles are internally self-timed and are initiated by the rising edge of
the clock (K) input. This feature eliminates complex off-chip write pulse gen-
eration and provides increased flexibility for incoming signals.
Dual write enables (LW and UW) are provided to allow individually writeable
bytes. LW controls DO~ - D08 (the lower bits), while UW controls D09 -
D017 (the upper bits).
0010
Vee
Vss
0011
0012
0013
0014
Vss
Vee
0015
0016
0017
This device is ideally suited for systems that require wide data bus widths
and cache memory. See Figure 2 for applications information.
• Single 5 V ± 5% Power Supply
• Fast Access Times: 9/12118 ns Max
• Byte Writeable via Dual Write Enables
• Internal Input Registers (Address, Data, Control)
• Internally Self-Timed Write Cycle
• ADSP, ADSC, and ADV Burst Control Pins
• Asynchronous Output Enable Controlled Three-State Outputs
• Common Data Inputs and Data Outputs
• 3.3 V I/O Compatible
• High Board Density 52-Lead PLCC Package
FN PACKAGE
PLASTIC
CASE 778
PIN ASSIGNMENT
IUID.c":,(r-c-:(lwl;=:>l~ c~:(~cE:(1ic:(~ ICJcC:(X)c:"( 'c~:(
7 6 5 4 3 2 1 52 51 50494847
8 46
9 45
10 44
11 43
12 42
13 41
14 40
15 39
16 38
17 37
18 36
19 35
20 34
21 22 23 24 25 26 27 28 29 30 31 32 33
~=f~~<~~~~~~~~
D08
D07
006
Vee
VSS
DOS
004
D03
D02
VSS
Vee
001
000
PIN NAMES
AD - A15 ................ Address Inputs
K ............................... Clock
ADV ....... . . . .. Burst Address Advance
LW ............ Lower Byte Write Enable
UW . . . . . . . . . . .. Upper Byte Write Enable
ADSC ......... Controller Address Status
ADSP . . . . . . . .. Processor Address Status
E . . . . . . . . . . . . . . . . . .. . . . . .. Chip Enable
G ...................... Output Enable
DOD - 0017 . . .. . . . . .. Data Input/Output
VCC ................ + 5 V Power Supply
VSS .......................... Ground
All power supply and ground pins must be
connected for proper operation of the device.
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.
This document contains Information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
MCM678618
4-218
MOTOROLA FAST SRAM DATA
1 page  
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level. . . . . . . . . . . . . .. 1.5 V
Input Pulse Levels .... .. .. .. . .. .. . . .. .. . . . . . . . .. . .. 0 to 3.0 V
Input Rise/Fall Time ...•................................ 3 ns
Output Timing Reference Level .. . . .. . . . .. .. . . . .. . . .. . . .. 1.5 V
Output Load ............ See Figure 1A Unless Otherwise Noted
READIWRITE CYCLE TIMING (See Notes 1, 2, and 3) (W refers to either or both byte write enables)
Symbol
MCM67B618-9 MCM67B618-12 MCM67B618-18
Parameter
Cycle Time
Clock Access Time
Output Enable to Output Valid
Clock High to Output Active
Clock High to Output Change
Output Enable to Output Active
Standard Alternate Min Max Min Max Min Max Unit Notes
tKHKH
tCYC
15
-
20 -
30 - ns
tKHQV
tCD
-
9-
12 -
18 ns 4
tGLOV
tOE
-
5-
6-
7 ns
tKHOX1
tDC1
6
-
6-
6 - ns
tKHOX2 tOC2 3 -
3-
3 - ns
tGLOX toLZ 0 -
0-
0 - ns
Output Disable to 0 High-Z
tGHOZ
tOHZ
2
6
2
7
2
7 ns 5
Clock High to 0 High-Z
tKHOZ
tcz
-
6-
6-
6 ns
Clock High Pulse Width
tKHKL
tCH
5-
6-
7 - ns
Clock Low Pulse Width
tKLKH
tCL
5-
6-
7 - ns
Setup Times:
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
tAVKH
tAOSVKH
tOVKH
twvKH
tAOVVKH
tEVKH
Address
Address Status
Data In
Write
Address Advance
Chip Enable
tKHAX
tKHAOSX
tKHDX
tKHWX
tKHAOVX
tKHEX
tAS
tss
tos
tws
tAH
tSH
tOH
twH
2.5 -
0.5 -
K~2.5 -
- ns 6
Ie;-:::-..
0.5 -
- ns 6
NOTES:
1. A read cycle is defined by UW and LW high or AOSP low for the setup and hold times. A write cycle is defined by LW or UW low and AOSP
high for the setup and hold times.
2. All read and write cycle timings are referenced from K or G.
3. G Is a don't care when UW or [W is sampled low.
4. Maximum access times are guaranteed for all possible i486 external bus cycles.
5. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled rather than 100% tested. At
any given voltage and temperature, tKHOZ max is less than tKHOZ1 min for a given device and from device to device.
6. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of K whenever AOSP or AOSC
is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of K when
the chip is enabled.Chip enable must be valid at each rising edge of clock for the device (when AOSP or ADSC is low) to remain enabled.
AC TEST LOADS
l-1OUTPUT!
: zo= son
RL =son
~OUTPUT
255 n
+5V480n
5pF
(INCLUDING
SCOPE AND JIG)
Figure 1A
Figure 18
NOTE: For information on output I-V characteristics, see Chapter 8, Section 1.
MCM67B618
4·222
MOTOROLA FAST SRAM DATA
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| PDF Descargar | [ Datasheet MCM67B618.PDF ] | |
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