|
|
PDF MCM67H618 Data sheet ( Hoja de datos )
| Número de pieza | MCM67H618 | |
| Descripción | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MCM67H618 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
|
No Preview Available !
MOTOROLA
• SEMICONDUCTOR
TECHNICAL DATA
MCM67H618
Product Preview
64K x 18 Bit BurstRAMTM
Synchronous Fast Static RAM
With Burst Counter and Self-Timed Write
The MCM67H618 is a 1,179,648 bit synchronous fast static random access memory
designed to provide a burstable, high-performance, secondary cache for the i486 and
Pentium™ microprocessors. It is organized as 65,536 words of 18 bits, fabricated with
Motorola's high-performance silicon-gate BiCMOS technology. The device integrates
input registers, a 2-bit counter, high speed SRAM, and high drive capability outputs onto
a single monolithic circuit for reduced parts count implementation of cache data RAM
applications. Synchronous design allows precise cycle control with the use of an
external clock (K). BiCMOS circuitry reduces the overall power consumption of the
integrated functions for greater reliability.
Addresses (AO - A15), data inputs (DO - 017), and all control signals except
output enable (G) are clock (K) controlled through positive-edge-triggered
nonInverting registers.
Bursts can be initiated with either address status processor (ADSP) or
address status cache controller (ADSC) input pins. Subsequent burst ad-
dresses can be generated internally by the MCM67H618 (burst sequence
D09
0010
Vee
Vss
imitates that of the i486 and Pentium) and controlled by the burst address
0011
advance (ADV) input pin. The following pages provide more detailed infor-
mation on burst controls.
Write cycles are internally self-timed and are Initiated by the rising edge of
the clock (K) input. This feature eliminates complex off-chip write pulse gen-
eration and provides increased flexibility for incoming signals.
Dual write enables (LW and 'OW) are provided to allow individually writeable
bytes. LW controls 000 - 008 (the lower bits), while UW controls 009 -
DQ17 (the upper bits).
D012
D013
D014
Vss
Vee
D015
D016
D017
This device is ideally suited for systems that require wide data bus widths
and cache memory. See Figure 2 for applications information.
• Single 5 V ± 5% Power Supply
• Fast Access Times: 9/12118 ns Max
• Byte Writeable via Dual Write Enables
• Internal Input Registers (Address, Data, Control)
• Internally Self-Timed Write Cycle
• ADSP, ADSC, and ADV Burst Control Pins
• Asynchronous Output Enable Controlled Three-State Outputs
• Common Data Inputs and Data Outputs
3.3 V 1/0 Compatible
• High Board Density 52-Lead PLCC Package
• A'DSP Disabled with Chip Enable (i:) - Supports Address Pipelining
FN PACKAGE
PLASTIC
CASE 778
PIN ASSIGNMENT
IUICL
<cor<--lwl=:>:l~ 8< 8<EI<:ilo: I~I<X)<"'<~
7 6 5 4 3 2 1 52 51 50494847
46
45
44
43
12 42
13 41
14 40
15 39
16 3B
17 37
lB 36
19 35
20 34
21 22 23 24 25 26 27 2B 29 30 31 32 33
DOB
D07
D06
Vee
VSS
D05
D04
D03
D02
Vss
Vee
DOl
DOO
PIN NAMES
AO - A15 ................ Address Inputs
K ............................... Clock
ADV ............ Burst Address Advance
LW ............ Lower Byte Write Enable
UW . . . . . . . . . . .. Upper Byte Write Enable
ADSC ......... Controller Address Status
ADSP . . . . . . . .. Processor Address Status
E . .. . . . . . . . . . . . . . . . . . . . . .. Chip Enable
G ...................... Output Enable
000 - 0017 . . . . . . . . .. Data Input'Output
VCC .... " .......••. + 5 V Power Supply
VSS .......................... Ground
All power supply and ground pins must be
connected for proper operation of the device.
BurstRAM is a trademark of Motorola, Inc.
i4B6 and Pentium are trademarks oOntel Corp.
This document contains Information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
MCM67H618
4-236
MOTOROLA FAST SRAM DATA
1 page  
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level. . . . . . . . . . . . . .. 1.5 V
aInput Pulse Levels •. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. to 3.0 V
Input Rise/Fall Time .................................... 3 ns
Output Timing Reference Level ........................ " 1.5 V
Output Load ............ See Figure 1A Unless Otherwise Noted
READIWRITE CYCLE TIMING (See Notes 1, 2, and 3) (Vii refers to either or both byte write enables)
Symbol
MCM67H618-9 MCM67H618-12 MCM67H618-18
Parameter
Cycle Time
Clock Access TiAle
Output Enable to Output Valid
Clock High to Output Active
Clock High to Output Change
Output Enable to Output Active
Standard Alternate Min Max Min Max Min Max Unit Notes
-tKHKH
tCYC
15
20 -
30 - ns
tKHQV
tCD
-
9-
12 -
18 ns 4
tGLQV
toE
-
5-
6-
7 ns
-tKHQX1
tDC1
6
6-
6 - ns
tKHQX2
tDC2
3
-
3-
3 - ns
tGLQX
toLz
a-
a-
a - ns
Output Disable to Q High-Z
tGHQZ
tOHZ
2
6
2
7
2
7 ns 5
Clock High to Q High-Z
tKHQZ
tcz
-
6-
6-
6 ns
Clock High Pulse Width
tKHKL
tCH
5-
6-
7 - ns
Clock Low Pulse Width
tKLKH
tCL
5-
6-
7 - ns
Setup Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
tAVKH
tADSVKH
tDVKH
twvKH
tADVVKH
tEVKH
tAS
tss
tDS
tws
2.5 -
2.5 -
3.0 -
ns 6
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
tKHAX
tKHADSX
tKHDX
tKHWX
tKHADVX
tKHEX
tAH
tSH
tDH
twH
0.5 -
0.5 -
0.5 -
ns 6
NOTES:
1. A read cycle is defined by UW and [iN high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and ADSP
high for the setup and hold times.
2. All read and write cycle timings are referenced from K or G.
3. G is a don't care when UW or LW is sampled low.
4. Maximum access times are guaranteed for all possible i486 external bus cycles.
5. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled rather than 100% tested.
At any given voltage and temperature, tKHQZ max is less than tKHQZ1 min for a given device and from device to device.
6. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of K whenever ADSP or
ADSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of
K when the chip is enabled.Chip enable must be valid at each rising edge of clock for the device (when ADSP or ADSC is low) to remain
enabled.
1OUTPUT
AC TEST LOADS
1 fZo = 50 n
~
RL = 50 n
~OUTPUT
255 n
+5V480n
5pF
(INCLUDING
SCOPE AND JIG)
Figure1A
Figure 18
NOTE: For information on output I-V characteristics, see Chapter 8, Section 1.
MCM67H618
4-240
MOTOROLA FAST SRAM DATA
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MCM67H618.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MCM67H618 | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM | Motorola Semiconductors |
| MCM67H618A | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM | Motorola Semiconductors |
| MCM67H618B | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM | Motorola Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |