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PDF MCM67Q709 Data sheet ( Hoja de datos )
| Número de pieza | MCM67Q709 | |
| Descripción | 128K x 9 Bit Separate I/O Synchronous Fast Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
• SEMICONDUCTOR
TECHNICAL DATA
Product Preview
128K x 9 Bit Separate 1/0
Synchronous Fast Static RAM
The Motorola MCM670709 is a 1,179,648 bit static random access memory,
organized as 131,072 words of 9 bits. This device is fabricated using Motorola's
high-performance silicon-gate BiCMOS technology. It features separate TTL input
and output buffers, which are fully I/O compatible at 3.3 V, and incorporates input
and output registers on board with high speed SRAM. It also features transparent-
write and data pass-through capabilities.
The synchronous design allows for precise cycle control with the use of an exter-
nal single clock (K). The Addresses (AO - A16), Data Input (DO - 08), Data Output
(00 - 08), Write-Enable (W), Chip-Enable (E), and Output-Enable (<3), are regis-
tered in on the rising edge of Clock (K).
The MCM670709 is available in a 9 x 10 grid, 86 bump surface mount OMPAC.
• Single 5 V ± 10% Power Supply
• Fast Cycle Times: 10/12 ns Max
• Single Clock Operation
• TTL Input and Output Levels (3.3 V I/O Compatible)
• Address, Data Input, E, W, G, Registers on Chip
• 100 MHz Maximum Clock Cycle Time
• Self Timed Write
• Separate Data Input and Output Pins
• Transparent-Write or Data Pass-Through
• High Output Drive Capability: 50 pF/Output at Rated Access Time
• Boundary Scan Implementation
MCM67Q709
9x 10 GRID
86 BUMP OMPAC
CASE 896A-Q1
PIN NAMES
AO - A16 ................. Address Input
E. . . . . . . . . . . . . . . .. . . . . . . .. Chip Enable
W ........................ Write Enable
G ...................... Output Enable
DO - 08 .................... Data Inputs
00 - 08 .................. Data Outputs
K .......................... Clock Input
TCK ..................• Test Clock Input
TMS .......•.......•.. Test Mode Select
TDI ........•..........•. Test Data Input
TOO .................. Test Data Output
VCC .• . . . . . •. . . . . .. + 5 V Power Supply
VSS .......................... Ground
NC ..................... No Connection
Il
~
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
MOTOROLA FAST SRAM DATA
MCM67Q709
4-281
1 page  
AC OPERATING CONDITIONS AND CHARACTERISTICS
= =(Vee 5.0 V ± 10%, TA 0 to + 70oe, Unless Otherwise Noted)
Input Timing Measurement Reference Level ............... 1.5 V
Input Pulse Levels. . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . .. 0 to 3.0 V
Input Rise/Fall Time .................................... 3 ns
Output Timing Reference Level . . . . . . . . . .. .. . . . . . . . . . . . .. 1.5 V
Output Load ................ Figure 1A Unless Otherwise Noted
READIWRITE CYCLE TIMING (See Notes 1, 2, and 3)
Symbol
MCM67Q709-10
MCM67Q709-12
Parameter
Standard Alternate
Min
Max
Min
Max Unit Notes
Cycle Time
Clock Access Time
Clock Low Pulse Width
Clock High Pulse Width
Clock High to Data Output Invalid
Clock High to Data Output High-Z
Setup Times:
A
W
E
G
00-08
Hold Times:
A
W
E
G
00-08
tKHKH
tKHQV
tKLKH
tKHKL
tKHQX
tKHQZ
tAVKH
twvKH
tEVKH
IGVKH
tOVKH
tKHAX
tKHWX
tKHEX
tKHGX
tKHOX
tCYC
tco
tCL
tCH
tOC1
tcz
tAS
tws
tES
tGS
tos
tAH
twH
tEH
tGH
tOH
10 -
-5
4-
4-
2-
-5
2-
1-
12 - ns 1
- 6 ns 2
4 - ns
4 - ns
2 - ns
- 6 ns
2 - ns 3
1 - ns 3
NOTES:
1. All read and write cycles are referenced from K.
2. Valid data from Clock High will be the data stored at the address or the last valid read cycle.
3. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL rising
edges of clock (K) while the device is selected.
AC SPEC LOADS
II
0fOUTPUT---:t
-= Zo= son ::-
50
"
~+5V48onOUTPUT
255 n
5pF
(INCLUDING
SCOPE AND JIG)
Figure 1A
Figure 18
MOTOROLA FAST SRAM DATA
MCM67Q709
4-285
5 Page | ||
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| PDF Descargar | [ Datasheet MCM67Q709.PDF ] | |
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