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PDF MCM72BA64 Data sheet ( Hoja de datos )
| Número de pieza | MCM72BA64 | |
| Descripción | 256KB and 512KB BurstRAM Secondary Cache Module | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
256KB and 512KB BurstRAM™
Secondary Cache Module for
Pentium™
The MCM72BA32SG and MCM72BA64SG are designed to provide a burst-
able, high performance, 256K/512K L2 cache for the Pentium microprocessor.
The modules are configured as 32K x 72 and 64K x 72 bits in a 136 pin dual read-
out single inline memory module (DIMM). The module uses four of Motorola’s
MCM67B518 or MCM67B618 BiCMOS BurstRAMs.
Bursts can be initiated with either address status processor (ADSP) or address
status controller (ADSC). Subsequent burst addresses are generated internal to
the BurstRAM by the burst advance (ADV) input pin.
Write cycles are internally self timed and are initiated by the rising edge of the
clock (K) input. Eight write enables are provided for byte write control.
The cache family is designed to interface with popular Pentium cache control-
lers with on board TAG.
PD0 – PD2 are reserved for density and speed identification.
• Pentium–style Burst Counter on Board
• Dual Readout SIMM for Circuit Density
• Single 5 V ± 5% Power Supply
• All Inputs and Outputs are TTL Compatible
• Three State Outputs
• Byte Parity
• Byte Write Capability
• Fast Module Clock Rates: 66 MHz, 60 MHz, 50MHz
• Decoupling Capacitors for each Fast Static RAM
• High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
• I/Os are 3.3 V Compatible
Order this document
by MCM72BA32/D
MCM72BA32
MCM72BA64
136–LEAD DIMM
CASE 1104–01
TOP VIEW
1
34
35
68
BurstRAM is a trademark of Motorola.
Pentium is a trademark of Intel Corp.
REV 2
5/95
M© OMoTtoOroRla,OInLc.A19F95AST SRAM
MCM72BA32•MCM72BA64
1
1 page  
K
ADSC
ADSP
A0 – A15
MCM67B618 BLOCK DIAGRAM (See Note)
ADV BURST LOGIC
Q0
A0
Q1
CLR
A1
INTERNAL
ADDRESS
A0′
16
A1′
64K × 18
MEMORY
ARRAY
ADDRESS
REGISTER
2
A1 – A0
A2 – A15
16
18 9 9
WRITE
UW REGISTER
LW
DATA–IN
REGISTERS
E
G
DQ0 – DQ8
DQ9 – DQ17
9
9
ENABLE
REGISTER
99
OUTPUT
BUFFER
NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is per-
formed using the new external address. Alternatively, an ADSP–initiated two cycle WRITE can be performed by asserting
ADSP and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW with valid
data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram).
When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent
on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded.
After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address
is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait
state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See
BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW).
BURST SEQUENCE TABLE (See Note)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A15 – A2
A15 – A2
A15 – A2
A15 – A2
A1
A1
A1
A1
A0
A0
A0
A0
NOTE: The burst wraps around to its initial state upon completion.
MOTOROLA FAST SRAM
MCM72BA32•MCM72BA64
5
5 Page 
K
ADSP
ADDRESS
LW, UW
ADV
tADSVKH
COMBINATION READ/WRITE CYCLE
tKHKH
tKHADSX tKHKL
tKLKH
tAVKH
tKHAX
A1
A2
tWVKH
tADVVKH
A3
tKHWX
tKHADVX
G
DATA IN
DATA OUT
tKHQV
tKHQX1
Q(A1)
READ
tDVKH
tGHQZ
D(A2)
tKHDX
tGLQX
WRITE
tGLQV
tKHQX2
Q(A3) Q(A3 + 1) Q(A3 + 2)
BURST READ
MOTOROLA FAST SRAM
MCM72BA32•MCM72BA64
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet MCM72BA64.PDF ] | |
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