PDF ADF41020 Data sheet ( Hoja de datos )

Número de pieza	ADF41020
Descripción	18 GHz Microwave PLL Synthesizer
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet 18 GHz Microwave PLL Synthesizer ADF41020 FEATURES 18 GHz maximum RF input frequency Integrated SiGe prescaler Software compatible with the ADF4106/ADF4107/ADF4108 family of PLLs 2.85 V to 3.15 V PLL power supply Programmable dual-modulus prescaler 8/9, 16/17, 32/33, 64/65 Programmable charge pump currents 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode 4000 V HBM/1500 V CDM ESD performance APPLICATIONS Microwave point-to-point/multipoint radios Wireless infrastructure VSAT radios Test equipment Instrumentation GENERAL DESCRIPTION The ADF41020 frequency synthesizer can be used to implement local oscillators as high as 18 GHz in the up conversion and down conversion sections of wireless receivers and transmitters. It consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, and high frequency programmable feedback dividers (A, B, and P). A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). The synthesizer can be used to drive external microwave VCOs via an active loop filter. Its very high bandwidth means a frequency doubler stage can be eliminated, simplifying system architecture and reducing cost. The ADF41020 is software-compatible with the existing ADF4106/ADF4107/ADF4108 family of devices from Analog Devices, Inc. Their pinouts match very closely with the exception of the ADF41020’s single-ended RF input pin, meaning only a minor layout change is required when updating current designs. REFIN AVDD DVDD FUNCTIONAL BLOCK DIAGRAM VP GND R COUNTER PHASE FREQUENCY DETECTOR REFERENCE RSET CHARGE PUMP CP CLK DATA LE 24-BIT INPUT REGISTER R COUNTER LATCH FUNCTION LATCH A, B COUNTER LATCH RFIN 3pF 50Ω N = 4(BP + A) DIVIDE BY 4 P/P+ 1 A AND B COUNTERS LOCK DETECT CURRENT SETTING 1 CURRENT SETTING 2 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 AVDD SDOUT MUX HIGH-Z MUXOUT M3 M2 M1 ADF41020 GND CE GND Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND AVDD to DVDD VP to GND VP to AVDD Digital I/O Voltage, REFIN to GND Analog I/O Voltage to GND REFIN, RFIN to GND Operating Temperature Range Industrial Storage Temperature Range Maximum Junction Temperature LFCSP θJA Thermal Impedance1 (Paddle Soldered) Reflow Soldering Peak Temperature Time at Peak Temperature Transistor Count CMOS Bipolar ESD (Charged Device Model) ESD (Human Body Model) Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to VP + 0.3 V −0.3 V to AVDD + 0.3 V −40°C to +85°C −65°C to +125°C 150°C 62.82°C/W 260°C 40 sec 6610 358 1500 V 4000 V 1 Two signal planes (that is, on the top and bottom surfaces of the board), two buried planes, and four vias. ADF41020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. B \| Page 5 of 16 5 Page Data Sheet ADF41020 RESERVED 13-BIT B COUNTER 6-BIT A COUNTER CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1) B13 B12 B11 B3 B2 B1 00 00 00 00 .. .. .. 11 11 11 11 0 .......... 0 0 .......... 0 0 .......... 0 0 .......... 0 . .......... . . .......... . . .......... . 1 .......... 1 1 .......... 1 1 .......... 1 1 .......... 1 00 01 10 11 .. .. .. 00 01 10 11 A COUNTER A6 A5 .......... A2 A1 DIVIDE RATIO 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 60 1 1 .......... 0 1 61 1 1 .......... 1 0 62 1 1 .......... 1 1 63 B COUNTER DIVIDE RATIO NOT ALLOWED NOT ALLOWED 2 3 . . . 8188 8189 8190 8191 F4 (FUNCTION LATCH) FASTLOCK ENABLE 0 0 1 1 CP GAIN 0 1 0 1 OPERATION CHARGE PUMP CURRENT SETTING 1 IS PERMANENTLY USED. CHARGE PUMP CURRENT SETTING 2 IS PERMANENTLY USED. CHARGE PUMP CURRENT SETTING 1 IS USED. CHARGE PUMP CURRENT IS SWITCHED TO SETTING 2. THE TIME SPENT IN SETTING 2 IS DEPENDENT ON WHICH FAST LOCK MODE IS USED. SEE FUNCTION LATCH DESCRIPTION. N = 4(BP + A), P IS A PRESCALER VALUE SET IN THE FUNCTION LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF (N × FREF), AT THE OUTPUT, N MIN IS 4(P2 – P). BOTH OF THESE BITS MUST BE SET TO 0 FOR NORMAL OPERATION. Figure 16. N (A, B) Counter Latch Map Rev. B \| Page 11 of 16 11 Page

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