|
|
PDF TMPM333FYFG Data sheet ( Hoja de datos )
| Número de pieza | TMPM333FYFG | |
| Descripción | 32-bit RISC Microprocessor | |
| Fabricantes | Toshiba | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de TMPM333FYFG (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
32 Bit RISC Microcontroller
TX03 Series
TMPM333FDFG/FYFG/FWFG
1 page  
TMPM333FDFG/FYFG/FWFG
1.2.2 SAMCR(Control register)
31 30 29 28 27
bit symbol
-
-
-
-
-
After reset
0
0
0
0
0
23 22 21 20 19
bit symbol
-
-
-
-
-
After reset
0
0
0
0
0
15 14 13 12 11
bit symbol
-
-
-
-
-
After reset
0
0
0
0
0
76543
bit symbol
MODE
TDATA
After reset
0
0
0
1
0
Bit
31-10
9-7
6-0
Bit Symbol
−
MODE[2:0]
TDATA[6:0]
Type
R
R/W
W
"0" can be read.
Operation mode settings
000 : Sample mode 0
001 : Sample mode 1
010 : Sample mode 2
011 : Sample mode 3
The settings other than those above: Reserved
Transmitted data
Function
Note: The Type is divided into three as shown below.
26
-
0
18
-
0
10
-
0
2
0
25 24
--
00
17 16
--
00
98
MODE
00
10
00
R/W
R
W
READ WRITE
READ
WRITE
c. Data descriptopn
Meanings of symbols used in the SFR description are as shown below.
・ x:channel numbers/ports
・ n,m:bit numbers
d. Register descriptoption
Registers are described as shown below.
・ Register name <Bit Symbol>
Exmaple: SAMCR<MODE>="000" or SAMCR<MODE[2:0]>="000"
<MODE[2:0]> indicates bit 2 to bit 0 in bit symbol mode (3bit width).
・ Register name [Bit]
Example: SAMCR[9:7]="000"
It indicates bit 9 to bit 7 of the register SAMCR (32 bit width).
5 Page 
7.1.2.1 Exception Request and Detection
7.1.2.2 Exception Handling and Branch to the Interrupt Service Routine (Pre-emption)
7.1.2.3 Executing an ISR
7.1.2.4 Exception exit
7.2 Reset Exceptions......................................................................................................................61
7.3 Non-Maskable Interrupts (NMI)..............................................................................................62
7.4 SysTick....................................................................................................................................62
7.5 Interrupts..................................................................................................................................63
7.5.1 Interrupt Sources................................................................................................................................................................63
7.5.1.1 Interrupt Route
7.5.1.2 Generation
7.5.1.3 Transmission
7.5.1.4 Precautions when using external interrupt pins
7.5.1.5 List of Interrupt Sources
7.5.1.6 Active level
7.5.2 Interrupt Handling..............................................................................................................................................................67
7.5.2.1 Flowchart
7.5.2.2 Preparation
7.5.2.3 Detection by Clock Generator
7.5.2.4 Detection by CPU
7.5.2.5 CPU processing
7.5.2.6 Interrupt Service Routine (ISR)
7.6 Exception/Interrupt-Related Registers.....................................................................................72
7.6.1 Register List.......................................................................................................................................................................72
7.6.2 NVIC Registers..................................................................................................................................................................73
7.6.2.1 SysTick Control and Status Register
7.6.2.2 SysTick Reload Value Register
7.6.2.3 SysTick Current Value Register
7.6.2.4 SysTick Calibration Value Register
7.6.2.5 Interrupt Set-Enable Register 1
7.6.2.6 Interrupt Set-Enable Register 2
7.6.2.7 Interrupt Clear-Enable Register 1
7.6.2.8 Interrupt Clear-Enable Register 2
7.6.2.9 Interrupt Set-Pending Register 1
7.6.2.10 Interrupt Set-Pending Register 2
7.6.2.11 Interrupt Clear-Pending Register 1
7.6.2.12 Interrupt Clear-Pending Register 2
7.6.2.13 Interrupt Priority Register
7.6.2.14 Vector Table Offset Register
7.6.2.15 Application Interrupt and Reset Control Register
7.6.2.16 System Handler Priority Register
7.6.2.17 System Handler Control and State Register
7.6.3 Clock generator registers...................................................................................................................................................91
7.6.3.1 CGIMCGA(CG Interrupt Mode Control Register A)
7.6.3.2 CGIMCGB(CG Interrupt Mode Control Register B)
7.6.3.3 CGIMCGC(CG Interrupt Mode Control Register C)
7.6.3.4 CGICRCG(CG Interrupt Request Clear Register)
7.6.3.5 CGNMIFLG(NMI Flag Register)
7.6.3.6 CGRSTFLG (Reset Flag Register)
8. Input/Output Ports
8.1 Port Functions........................................................................................................................101
8.1.1 Function Lists..................................................................................................................................................................101
8.1.2 Port Registers Outline......................................................................................................................................................104
8.1.3 Port States in STOP Mode...............................................................................................................................................105
8.1.4 Precautions for Mode Transition between STOP and SLEEP.........................................................................................105
8.2 Port functions.........................................................................................................................106
8.2.1 Port A (PA0 to PA7)........................................................................................................................................................106
8.2.1.1 Port A Circuit Type
8.2.1.2 Port A register
8.2.1.3 PADATA (Port A data register)
8.2.1.4 PACR (Port A output control register)
8.2.1.5 PAFR1 (Port A function register 1)
8.2.1.6 PAPUP (Port A pull-up control register)
8.2.1.7 PAPDN (Port A pull-down control register)
8.2.1.8 PAIE (Port A input control register)
8.2.2 Port B (PB0 to PB7).........................................................................................................................................................111
8.2.2.1 Port B Circuit Type
iii
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TMPM333FYFG.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| TMPM333FYFG | 32-bit RISC Microprocessor | Toshiba |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |