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PDF CDP1855 Data sheet ( Hoja de datos )
| Número de pieza | CDP1855 | |
| Descripción | 8-Bit Programmable Multiply/Divide Unit | |
| Fabricantes | GE | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CDP1855 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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CMOS Peripherals - - - - - - - - - - - - - - - - - - - - - - - - - - -
CDP1855, CDP1855C
eE
CLEAR
ell
co/OF
Yl
ZL
mnn
elK
ST8
ROI'W"E:
RA 2
RAI
RAil
VSS
28 Vee
27 CNe
cr26 CN I
4 25
5 24 YR
6 23 ZR
7 22 BUS 7
8 21 BUS 6
9 20 BUS 5
10 19 BUS 4
II 18 BUS 3
12 17 BUS 2
13 16 suS I
14 15 BUSg
TOP VIEW
92CS- 2996!5R2
TERMINAL ASSIGNMENT
8-Bit Programmable
Multiply/Divide Unit
Features:
• Cascadable up to 4 units for 32-bit by 32-bit multiply or64 -7- 32 bit divide
• 8-blt by 8-bit multiply or 16 -7- 18 bit divide in 5.6 jJs at 5 Vor 2.8 jJs at 10 V
• Direct interface to CDP1800 series microprocessors
• Easy interface to other 8-bit microprocessors
• Significantly increases throughput of microprocessor used for
arithmetic calculations
The RCA-CDP1855 and CDP1855C are CMOS 8-bit
multiply/divide units which can be used to greatly increase
the capabilities of 8-bit microprocessors. They perform
multiply and divide operations on unsigned, binary
operators. In general, microprocessors do not contain
multiple or divide instructions and even efficiently coded
multiply or divide subroutines require considerable memory
and execution time. These multiply/divide units directly
interface to the CDP1800 series microprocessors via the
N-lines and can easily be configured to fit in either the
memory or I/O space of other 8-bit microprocessors.
The multiple/divide unit is based on a method of multiplying
by add and shift right operations and dividing by subtract
and shift left operations. The device is structured to permit
cascading identical units to handle operands up to 32 bits.
The CDP1855 and CDP1855C are functionally identical.
They differ In that the CDP1855 has a recommended
operating voltage range of4 -10.5 volts, and the CDP1855C,
a recommended operating voltage range of 4 - 6.5 volts.
The CDP1855 and CDP1855C types are supplied in a 28-
lead hermetic dual-in-line ceramic package (D suffix) and
in a 28-lead dual-in-line plastic package (E suffix). The
CDP1855C is also available in chip form (H suffix).
1 +v
j
CLEAR
XTAl
•CLEAR
ClK
CE
NO RAO CI
NI RAI CNO
N2 RA2 CNI
TPB STB
MRD RD/WE
CDPI802
E YL CDPI855
ZR
CTl
IT
BUS
CO
C YR
Zl
BUS
Is 92CM-34331
FIg. 1 - CIfCUlt confIguratIOn for MDU addressed as an 110 deVIce.
File Number 1053
404 ____________________________________________________________
~
1 page  
CMOS Peripherals - - - - - - - - - - - - - - - - - - - - - - - - - - -
CDP1855, CDP1855C
OPERATION (Cont'd)
The Z register can simply be reset using bit 2 of the control
word and another divide can be done in order to further
divide the remainder.
Z register with Y being the more significant half and Z the
less significant half. The X register will be unchanged after
the operation IS completed
3. Multiply Operation
For a multiply operation the two numbers to be multiplied
are loaded in the X and Z registers The result is In the Yand
The original contents of the Y register are added to the
product of X and Z Bit 3 of the control word will reset
register Y to 0 If desired.
FUNCTIONAL DESCRIPTION OF CDP1855 TERMINALS
CE - CHIP ENABLE (Input):
CLK - CLOCK (Input):
A high on this pin enables the CDP1855 MDU to respond to
the select lines. All cascaded MDU's must be enabled
together. CE also controls the tristate C.O.lO.F., output of
the most significant MDU.
This pin should be grounded on all but the most Significant
MDU. There is an optional reduction of clock frequency
available on this pin if so desired, controlled by bit 7 of the
control byte.
CLEAR (Input):
STB - STROBE (Input):
The CDP1855 MDU(s) must be cleared upon power-on with
a low-on this pin. The clear signal resets the sequence
counters, the shift pulse generator, and bits 0 and 1 of the
control register.
CTL - CONTROL (Input):
This isan input pin. All CTL pins must be wired together and
to the YL of the most significant CDP1855 MDU and to the
ZR of the least significant CDP1855 MDU. This signal is
used to indicate whether the registers are to be operated on
or only shifted.
When RD/WE is low data is latched from bus lines on the
falling edge of this signal. It may be asynchronous to the
clock. Strobe also increments the selected register's
sequence counter dUring reads and writes. TPB would be
used in CDP1800 systems.
RD/WE - READ/WRITE ENABLE (Input):
This signal defines whether the selected re~r is to be
read from or written to. In 1800 systems use MRD if MDU's
are addressed as 1/0 devices, MWR is used if MDU's are
addressed as memory devices.
C.O.lO,F, - C:'A""R""'R"'Y""'O-=-=U=T/""O""'V-::E::':R""F"'L""'O""W"'" (Output):
RA2, RA1, RAO - REGISTER ADDRESS (Input):
This is a tristate output pin. It is the CDP1855 Carry Out
signal and is connected to Ci (CARRY-IN) of the next more
significant CDP1855 MDU, except for on the most significant
MDU. On that MDU it isan overflow indicator and is enabled
when chip enables is true. A low on this pin indicates that an
overflow has occured. The overflow signal is latched each
time the control register is loaded, but is only meaningful
after a divide command.
These Input signals define which register is to be read from
or written to. It can be seen In the "CONTROL TRUTH
TABLE" that RA2 can be used as a chip enable. It IS
identiflcal to the CE pin, except only CE controls the tristate
C O.lO.F on the most significant MDU. In 1800 systems use
N lines if MDU's are used as 1/0 devices, use address lines
or function of address lines if MDU's are used as memory
deVices.
YL, YR - Y-LEFT, Y-RIGHT:
BUS 0 - BUS 7 - BUS LINES:
These are tristate bi-directional pins for data transfer
between the Y registers of cascaded CDP1855 MDU's. The
YR pin is an output and YL is an input during a multiply and
the reverse is true at all other times. The YL pin must be
conneCted to the YR pin of the next more significant MDU.
An exception is that the YL pin of the most significant
CDP1855 MDU must be connected to the ZR pin olthe least
significant MDU and to the CTL pins of all MDU's. Also the
YR pin of the least significant MDU is tiexd to the ZL pin of
the most significant MDU.
ZL. ZR - Z-LEFT, Z-RIGHT:
These are tristate bi-directional pins for data transfers
between the "Z" registers of cascaded MDU's. The ZR pin is
an output and ZL is an input during a multiply and the
reverse is true at all other times. The ZL pin must be tied to
the YR pin of the next more significant MDU. An exception
is that the ZL pin of the most significant MDU must be
connected to the YR pin of the least significant MDU. Also,
the ZR pin olthe least significant MDU is tied to the YL of the
most significant MDU.
SHIFT - SHIFT CLOCK:
This is a tristate bi-directional pin. It is an output on the
most significant MDU. And an input on all other MDU's. It
provides the MDU system timing pulses. All SHIFT pins
must be connected together for cascaded operation. A
maximum of the 8N +1 shifts are required for an operation
where "N" equals the number of MDU devices that are
cascaded.
Tristate bl-directional bus for direct interface With CDP1800
series and other 8-bit microprocessors.
ZR - Z-RIGHT:
See Pin 6.
YR - Y-RIGHT:
See Pin 5.
CI- CARRY IN (Input):
ThiS is an input for the carry from the next less significant
MDU. On the least significant MDU it must be high (VDD)
on all others it must be connected to the CO pin of the next
less significant MDU
CN1, CNO - CHIP NUMBER (Input):
These two input pins are Wired high or low to indicate the
MDU position in the cascaded chain. Both are high for the
most significant MDU regardless of how many CDP1855
MDU's are used. Then CN1 = high and CNO = low for the
next MDU and so forth.
VSS - GROUND:
Power supply line.
VDD -V+'
Power supply line.
408 ____________________________________________________________________
5 Page 
CMOS Peripherals - - - - - - - - - - - - - - - - - - - - - - - - . . . , . " . . . .
CDP1855, CDP1855C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +850 C. VDD ±5"1e tro tf = 20 nl. VIH = 0.7 VDD. VIL =0.3 VDD.
CL = 100 pF (S.. Fig. 7)
CHARACTERISTIC-
VDD
(V)
LIMITS
CDP1855
CDP185&C
Min., TYP.., Mu. Min. , Typ.. , MIX.
UNI'J'S
Operation Timing
Maximum Clock Frequency+
Maximum Shift Frequency
(1 Device)A
Minimum Clock Width
Minimum Clock Period
Clock to Shift Prop. Delay
Minimum C.1. to Shift Setup
C.O. from Shift Prop. Delay
Minimum C.1. from Shift Hold
Minimum Register Input Setup
Reg ister after Sh ift Delay
Minimum Register after Shift Hold
C.O. from C.1. Prop. Delay
Register from C.1. Prop. Delay
tCLKO
tCLK1
tCLK
tCSH
tsu
tpLH
tPHL
tH
tsu
tPLH
tPHL
tH
tPLH
tPHL
tPLH
tpHL
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
- -3.2 4
3.2 4
6.4 8
1.6 2
-
-
--
1.6 2
-
-
MHz
3.2 4 - - - -
- 100 150
100 150
- -50 75 - -
- -250 312
250 312
- 125 156
-
-
-
- -200 300
200 300
100 150
-
-
-
- -50 67
50 67
- -25 33 - -
- -450 600
450 600
-
225 300
-
-
-
-- 50 75
- 25 40
50
-
75
-
ns
- --20 10
-20 10
- -10 10 - - -
- -400 600
400 600
-
200 300
-
-
-
50 100-
50 'fO!r
- -25 50 - -
- -100 150
100 150
- -50 75 - -
- -80 120
80 120
- 40 60
--
-Maximum limits of minimum characteristics are the values above which all devices function.
·Typical values are for TA = 250 C and nominal voltages.
+Clock frequency and pulse width are given for systems using the Internal clock option of the CDP1855. Clock frequency
equals shift frequency for systems not using the Internal clock option.
AShift period for cascading of devices Is Increased by an amount equal to the lIT. to c,o. Prop. Delay for each device added.
Fig. 7 - Operation timing diagram.
414 ______________________________________________________________
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet CDP1855.PDF ] | |
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