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PDF MT40A256M16 Data sheet ( Hoja de datos )
| Número de pieza | MT40A256M16 | |
| Descripción | DDR4 SDRAM | |
| Fabricantes | Micron | |
| Logotipo |  |
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DDR4 SDRAM
MT40A1G4
MT40A512M8
MT40A256M16
Features
• VDD = VDDQ = 1.2V ±60mV
• VPP = 2.5V, –125mV/+250mV
• On-die, internal, adjustable VREFDQ generation
• 1.2V pseudo open-drain I/O
• TC maximum up to 95°C
– 64ms, 8192-cycle refresh up to 85°C
– 32ms, 8192-cycle refresh at >85°C to 95°C
• 16 internal banks (x4, x8): 4 groups of 4 banks each
• 8 internal banks (x16): 2 groups of 4 banks each
• 8n-bit prefetch architecture
• Programmable data strobe preambles
• Data strobe preamble training
• Command/Address latency (CAL)
• Multipurpose register READ and WRITE capability
• Write and read leveling
• Self refresh mode
• Low-power auto self refresh (LPASR)
• Temperature controlled refresh (TCR)
• Fine granularity refresh
• Self refresh abort
• Maximum power saving
• Output driver calibration
• Nominal, park, and dynamic on-die termination
(ODT)
• Data bus inversion (DBI) for data bus
• Command/Address (CA) parity
• Databus write cyclic redundancy check (CRC)
• Per-DRAM addressability
• Connectivity test (x16)
• sPPR and hPPR capability
• JEDEC JESD-79-4 compliant
4Gb: x4, x8, x16 DDR4 SDRAM
Features
Options1
• Configuration
– 1 Gig x 4
– 512 Meg x 8
– 256 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (9mm x 11.5mm) – Rev. A
– 78-ball (9mm x 10.5mm) – Rev. B
• FBGA package (Pb-free) – x16
– 96-ball (9mm x 14mm) – Rev. A
– 96-ball (9mm x 14mm) – Rev. B
• Timing – cycle time
– 0.625ns @ CL = 22 (DDR4-3200)
– 0.682ns @ CL = 20 (DDR4-2933)
– 0.682ns @ CL = 21 (DDR4-2933)
– 0.750ns @ CL = 18 (DDR4-2666)
– 0.750ns @ CL = 19 (DDR4-2666)
– 0.833ns @ CL = 16 (DDR4-2400)
– 0.833ns @ CL = 17 (DDR4-2400)
– 0.937ns @ CL = 15 (DDR4-2133)
– 0.937ns @ CL = 16 (DDR4-2133)
– 1.071ns @ CL = 13 (DDR4-1866)
• Operating temperature
– Commercial (0° ≤ TC ≤ 95°C)
– Industrial (–40° ≤ TC ≤ 95°C)
– Revision
Marking
1G4
512M8
256M162
HX
RH
HA
GE
-062E
-068E
-068
-075E
-075
-083E
-083
-093E
-093
-107E
None
IT
:A
:B
Notes:
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
2. Not available on Rev. A.
3. Restricted and limited availability.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
4Gb: x4, x8, x16 DDR4 SDRAM
Features
Command Address Latency ........................................................................................................................ 59
Internal VREF Monitor ................................................................................................................................. 59
Maximum Power Savings Mode ................................................................................................................... 60
Mode Register 5 .............................................................................................................................................. 61
Data Bus Inversion ..................................................................................................................................... 62
Data Mask .................................................................................................................................................. 63
CA Parity Persistent Error Mode .................................................................................................................. 63
ODT Input Buffer for Power-Down .............................................................................................................. 63
CA Parity Error Status ................................................................................................................................. 63
CRC Error Status ......................................................................................................................................... 63
CA Parity Latency Mode .............................................................................................................................. 63
Mode Register 6 .............................................................................................................................................. 64
tCCD_L Programming ................................................................................................................................. 65
VREFDQ Calibration Enable .......................................................................................................................... 65
VREFDQ Calibration Range ........................................................................................................................... 65
VREFDQ Calibration Value ............................................................................................................................ 65
Truth Tables ................................................................................................................................................... 66
NOP Command .............................................................................................................................................. 69
DESELECT Command .................................................................................................................................... 69
DLL-Off Mode ................................................................................................................................................ 69
DLL-On/Off Switching Procedures .................................................................................................................. 71
DLL Switch Sequence from DLL-On to DLL-Off ........................................................................................... 71
DLL-Off to DLL-On Procedure .................................................................................................................... 73
Input Clock Frequency Change ....................................................................................................................... 74
Write Leveling ................................................................................................................................................ 75
DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 76
Procedure Description ................................................................................................................................ 77
Write Leveling Mode Exit ............................................................................................................................ 78
Command Address Latency ............................................................................................................................ 80
Low-Power Auto Self Refresh Mode ................................................................................................................. 85
Manual Self Refresh Mode .......................................................................................................................... 85
Multipurpose Register .................................................................................................................................... 87
MPR Reads ................................................................................................................................................. 88
MPR Readout Format ................................................................................................................................. 90
MPR Readout Serial Format ........................................................................................................................ 90
MPR Readout Parallel Format ..................................................................................................................... 91
MPR Readout Staggered Format .................................................................................................................. 92
MPR READ Waveforms ............................................................................................................................... 93
MPR Writes ................................................................................................................................................ 95
MPR WRITE Waveforms .............................................................................................................................. 96
MPR REFRESH Waveforms ......................................................................................................................... 97
Gear-Down Mode .......................................................................................................................................... 100
Maximum Power-Saving Mode ....................................................................................................................... 103
Maximum Power-Saving Mode Entry .......................................................................................................... 103
Maximum Power-Saving Mode Entry in PDA .............................................................................................. 104
CKE Transition During Maximum Power-Saving Mode ................................................................................ 104
Maximum Power-Saving Mode Exit ............................................................................................................ 104
Command/Address Parity .............................................................................................................................. 106
Per-DRAM Addressability .............................................................................................................................. 114
VREFDQ Calibration ........................................................................................................................................ 117
VREFDQ Range and Levels ........................................................................................................................... 118
VREFDQ Step Size ........................................................................................................................................ 118
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2014 Micron Technology, Inc. All rights reserved.
5 Page 
4Gb: x4, x8, x16 DDR4 SDRAM
Features
Figure 51: CA Parity Error Checking – SRE Attempt ........................................................................................ 109
Figure 52: CA Parity Error Checking – SRX Attempt ........................................................................................ 110
Figure 53: CA Parity Error Checking – PDE/PDX ............................................................................................ 110
Figure 54: Parity Entry Timing Example – tMRD_PAR ..................................................................................... 111
Figure 55: Parity Entry Timing Example – tMOD_PAR ..................................................................................... 111
Figure 56: Parity Exit Timing Example – tMRD_PAR ....................................................................................... 111
Figure 57: Parity Exit Timing Example – tMOD_PAR ....................................................................................... 112
Figure 58: CA Parity Flow Diagram ................................................................................................................ 113
Figure 59: PDA Operation Enabled, BL8 ........................................................................................................ 115
Figure 60: PDA Operation Enabled, BC4 ........................................................................................................ 115
Figure 61: MRS PDA Exit ............................................................................................................................... 116
Figure 62: VREFDQ Voltage Range ................................................................................................................... 117
Figure 63: Example of VREF Set Tolerance and Step Size .................................................................................. 119
Figure 64: VREFDQ Timing Diagram for VREF,time Parameter .............................................................................. 120
Figure 65: VREFDQ Training Mode Entry and Exit Timing Diagram ................................................................... 121
Figure 66: VREF Step: Single Step Size Increment Case .................................................................................... 122
Figure 67: VREF Step: Single Step Size Decrement Case ................................................................................... 122
Figure 68: VREF Full Step: From VREF,min to VREF,maxCase .................................................................................. 123
Figure 69: VREF Full Step: From VREF,max to VREF,minCase .................................................................................. 123
Figure 70: VREFDQ Equivalent Circuit ............................................................................................................. 124
Figure 71: Connectivity Test Mode Entry ....................................................................................................... 128
Figure 72: hPPR WRA – Entry ........................................................................................................................ 131
Figure 73: hPPR WRA – Repair and Exit ......................................................................................................... 132
Figure 74: hPPR WR – Entry .......................................................................................................................... 133
Figure 75: hPPR WR – Repair and Exit ............................................................................................................ 133
Figure 76: sPPR – Entry ................................................................................................................................. 136
Figure 77: sPPR – Repair, and Exit ................................................................................................................. 136
Figure 78: tRRD Timing ................................................................................................................................ 139
Figure 79: tFAW Timing ................................................................................................................................. 139
Figure 80: REFRESH Command Timing ......................................................................................................... 141
Figure 81: Postponing REFRESH Commands (Example) ................................................................................. 141
Figure 82: Pulling In REFRESH Commands (Example) ................................................................................... 141
Figure 83: TCR Mode Example1 ..................................................................................................................... 143
Figure 84: 4Gb with Fine Granularity Refresh Mode Example ......................................................................... 146
Figure 85: OTF REFRESH Command Timing ................................................................................................. 147
Figure 86: Self Refresh Entry/Exit Timing ...................................................................................................... 150
Figure 87: Self Refresh Entry/Exit Timing with CAL Mode ............................................................................... 151
Figure 88: Self Refresh Abort ......................................................................................................................... 152
Figure 89: Self Refresh Exit with NOP Command ............................................................................................ 153
Figure 90: Active Power-Down Entry and Exit ................................................................................................ 155
Figure 91: Power-Down Entry After Read and Read with Auto Precharge ......................................................... 156
Figure 92: Power-Down Entry After Write and Write with Auto Precharge ........................................................ 156
Figure 93: Power-Down Entry After Write ...................................................................................................... 157
Figure 94: Precharge Power-Down Entry and Exit .......................................................................................... 157
Figure 95: REFRESH Command to Power-Down Entry ................................................................................... 158
Figure 96: Active Command to Power-Down Entry ......................................................................................... 158
Figure 97: PRECHARGE/PRECHARGE ALL Command to Power-Down Entry .................................................. 159
Figure 98: MRS Command to Power-Down Entry ........................................................................................... 159
Figure 99: Power-Down Entry/Exit Clarifications – Case 1 .............................................................................. 160
Figure 100: Active Power-Down Entry and Exit Timing with CAL .................................................................... 160
Figure 101: REFRESH Command to Power-Down Entry with CAL ................................................................... 161
Figure 102: ODT Power-Down Entry with ODT Buffer Disable Mode .............................................................. 162
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2014 Micron Technology, Inc. All rights reserved.
11 Page | ||
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