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PDF CDP68HC68P1 Data sheet ( Hoja de datos )
| Número de pieza | CDP68HC68P1 | |
| Descripción | CMOS Single Port Input/Output | |
| Fabricantes | GE | |
| Logotipo |  |
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CMOS Peripherals
CDP68HC68P1
Advance Information
100
I D.
M ISO
MOS I
SCK
CE
DO
VSS
•• Voo
'5 D.
•• 02
13 03
" D'
" D'
.0 os
07
TOP VI EW
92C5-40410
TERMINAL ASSIGNMENT
CMOS Single Port Input/Output
Features:
• Fully static ope._ don
• 8-Bit I/O port - each bit can
• Operating voltage range 3-6 V
• Compatible with RCA/Motorola SPI bus
be individually programmed
as an input or output via an
• 2 external address pins tied to Voo or Vss
8-bit data direction register
to allow up to 4 devices to share the
• Programmable on-board
same chip enable
comparator
• Versatile bit-set and bit-clear capability
• Simultaneous transfer of
• Accepts either SCK clock polarity - SCK
compare information to CPU
voltage level is latched when chip enable
during read or write -
goes active
separate access not required
• All inputs are Schmitt- Trigger
The single port I/O is a serially addressed 8 bit Input/Output
port that allows byte or individual bit control. It consists of
three registers. an output buffer and control logic. Data is
shifted in and out of the port via a shift register that utilizes
the SPI (Serial.peripherallnterface) bus. The I/O port data
flow is controlled by the Data Direction Register and data is
stored in the Data Register that outputs or senses the logic
levels at the buffered 110 pins. All inputs. including the
serial interface are schmitt triggered. The device also
features a compare function that compares the data register
and port pin val ues for 4 programmable conditions and sets
a software accessible flag if the condition is satisfied. The
user also has the option of bit-set or bit-clear when writing
to the data register.
The CDP68HC66P1 is supplied in 16-lead, hermetiC. dual-
in-line side-brazed ceramic (D suffix). 16-lead dual-in-line
plastic (E suffix) and 16-lead, surface mount. (small outline),
plastic (M suffix) packages.
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE. (Voe)
(Voltage referenced to Vss terminal) .................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ........................................................... -0.5 to Vee +0.5 V
DC INPUT CURRENT, ANY ONE INPUT .................................................................... ±10 mA
POWER DISSIPATION PER PACKAGE (Pe):
For TA = -40 to +60°C (PACKAGE TYPE E) .............................................................. 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) ................................ Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +100°C (PACKAGE TYPE D) ............................................................. 500 mW
For TA = +100 to 125°C (PACKAGE TYPE D) ............................... Derate Linearly at 12 mW/oC to 200 mW
For TA = -40 to HO°C (PACKAGE TYPE M)* ............................................................. 400 mW
For TA = +70 to +85°C (PACKAGE TYPE M)* ................................ Derate Linearly at 6 mW/oC to 310 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D ............................................................................... -55 to +125°C
PACKAGE TYPE E, M ............................................................................. -40 to +85°C
STORAGE-TEMPERATURE RANGE (Tatg) ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1132 in. (1.59 ± 0.79 mm) from case for 10 s maximum .................................... +265°C
• Printed-circuit board mount: 57 mm x 57 mm minimum area x 1.6 mm thick G1 a epoxy glass. or equivalent.
File Number 1858
534 _________________________________________________________________
1 page  
CMOSPeriphe~ls __________________________________________________
CDP68HC68P1
Data Format
During write operations, the data byte that follows the
control byte is normally the data word that is transferred to
the data or data direction register. Control bits 2 and 3 (DFO
and DF1) change the interpetation of this data as listed
below. Note that one or more bits can be set or cleared in
either register without having to write to bits not requiring
change.
C03 C02
DF1 DFO
oX
o
for example,
OPERATION
Data following the control word will
be written to the selected register.
Data following the control word Is
a mask. Those bits which are a 1
will cause that register flip-flop to
be cleared to O. Those which are
a 0 will cause that register flip-flop
to be unchanged.
Data following the control word is
a mask. Those bits which are a 1
will cause that register flip-flop to
be set to 1; those which are a 0
will cause that register flip-flop
to be unchanged.
CONTROL
C07 C06 C05 1 0 X C01 COO
C07 C06 C05 1 1 1 C01 COO
C07 C06 C05 1 1 0 C01 COO
C07 C06 C05 1 1 X C01 COO
X = Don't Care
DATA
11110000
11110000
11110000
00000000
PREVIOUS
REGISTER
VALUE
10101010
10101010
10101010
10101010
NEW
REGISTER
VALUE
11110000
11111010
00001010
10101010
Addressing the Single Port I/O
The Serial Peripheral Interface (SPI) utilized by the I/O Port
is a serial synchronous bus for control and data transfers. It
consists of a SCK clock input pin that shifts data out of the
I/O port (MISO, MASTER IN, SLAVE OUT) and latches data
presented atthe input pin, MOSI (master out, slave in). Data
is transferring in most significant bit first. There isone SCK
clock for each bit transferred and bits are transferred in
groups of eight.
When the I/O port IS selected by bringing the chip enable
pin low, the logic level at the SCK input is sampled to
determine the internal latching and shift polarity for input
and output signals on the SPI. (See Fig. 3).
The first byte shifted in when the chip is selected is always
the control byte followed by one or more bytes that become
data or a mask for the data and data direction register. As
the control byte is being shifted in one the MOSI line, data
on the MOSI line shifts out. (See Fig. 4).
~----,~-------------------------------------------
SCK
OR
SCK
MOSI
C07 C06 cos coo C03 C02 COl COO
MISO
C07 C06 COS COO C03
DONTCARE
HIGH IMPEDANCE
COMPARE FLAG
92CS- 40400
INPUT
OUTPUT
FIg. 4 - Control byte.
538 _______________________________________________________________
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CDP68HC68P1.PDF ] | |
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