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PDF LXT332 Data sheet ( Hoja de datos )
| Número de pieza | LXT332 | |
| Descripción | Dual T1/E1 Line Interface Unit | |
| Fabricantes | Intel | |
| Logotipo |  |
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LXT332
Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation
Datasheet
The LXT332 is a fully integrated Dual Line Interface Unit (DLIU) for both 1.544 Mbps (T1) and
2.048 Mbps (E1) applications. It features B8ZS/HDB3 encoders and decoders, and a constant
low output impedance transmitter for high return loss. Transmit pulse shape is selectable for
various line lengths and cable types.
The LXT332 incorporates an advanced crystal-less digital jitter attenuator, switchable to either
the transmit or receive side. This eliminates the need for an external quartz crystal. It offers
both a serial interface (SIO) for microprocessor control and a hardware control mode for stand-
alone operation.
The LXT332 offers a variety of advanced diagnostic and performance monitoring features. It
uses an advanced double-poly, double-metal CMOS process and requires only a single 5-volt
power supply.
Applications
s PCM/Voice Channel Banks
s Data Channel Bank/Concentrator
s T1/E1 multiplexer
s Digital Access and Cross-connect Systems
(DACS)
s Computer to PBX interface (CPI & DMI)
s SONET/SDH Multiplexers
s Interfacing Customer Premises Equipment
to a CSU
s Digital Loop Carrier (DLC) terminals
Product Features
s Digital (crystal-less) jitter attenuation,
selectable for receive or transmit path, or
may be disabled
s High transmit and receive return loss
s Constant low output impedance transmitter
with programmable equalizer shapes pulses
to meet DSX-1 pulse template from 0 to
655 ft.
s Meets or exceeds industry specifications
including ITU G.703, ANSI T1.403, AT&T
Pub 62411 and ITU-T G.742
s Compatible with most industry standard
framers
s Complete line driver, data recovery and
clock recovery functions
s Minimum receive signal of 500 mV, with
selectable slicer levels to improve SNR
s Local, remote, and dual loopback functions
s Built-In Self Test with QRSS Pattern
Generator
s Transmit/Receive performance monitors
with Driver Fail Monitor (DFM) and Loss
of Signal (LOS) outputs
s Receiver jitter tolerance 0.4 UI from 40
kHz to 100 kHz
s Available in 44-pin PLCC and 44-pin QFP
packages
As of January 15, 2001, this document replaces the Level One document
LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation.
Order Number: 249075-001
January 2001
1 page  
Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332
Figure 1. LXT332 Block Diagram
TCLK
TPOS
TNEG
JASEL
QRSS / BPV Generator
B8ZS/HDB3
Unipolar
Encoder
Encoder
Enable
Decoder
Enable RLOOP
Remote
Loopback
Enable
Jitter
Attenuator
Local
Loopback
Transmit
Timing &
Control
TAOS
Enable
Serial Word
LLOOP
Enable
Equalizer
LEN Select
Monitor
DFM
Internal
Clock
Generator
RPOS
RNEG
RCLK
B8ZS/HDB3
Unipolar
Decoder
LOS
QRSS Detector
Timing &
Data
Recovery
LOS
Processor
Peak
Detector
Transceiver 0
Transceiver 1
Line
Driver
TTIP
TRING
DFM
Serial
Port
MCLK
HFC
RTIP
RRING
INT0/1
PS0/1
CLKE
SCLK
SDI
SDO
Datasheet
5
5 Page 
Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332
Table 1. Host Mode and Bipolar Host Mode Pin Descriptions (Continued)
Pin Pin
QFP PLCC
Symbol
I/O1
Description
7 13 GND S Ground. Ground return for the VCC power supply.
Transmit Tip and Ring - Port 0. These pins are differential driver outputs designed to
8
14
TTIP0
AO drive a 35 - 200 Ω load. Line matching resistors and transformers can be selected to
11 17 TRING0 AO give the desired pulse height. See Table 10 and Figure 14 through Figure 16 for
details.
9 15 TGND0 S Ground - Port 0 Transmit Driver. Ground return for the TVCC0 power supply.
10
16
TVCC0
S
+ 5 VDC - Port 0 Transmit Driver. TVCC0 must not vary from TVCC1 or VCC by more
than ± 0.3 V.
12 18
DFM
DO
Driver Failure Monitor. This signal goes High to indicate a driver output short in one
or both ports.
13 19
PS0
DI
Port Select - Port 0. This signal selects the serial interface registers for port 0. For
each read or write operation, PS0 must transition from High to Low, and remain Low.
14 20
PD0
Pattern Detect - Port 0. Unless the QRSS function is selected by the VCQE pin, PD0
functions as an Alarm Indication Signal (AIS). The AIS pattern is detected by the
receiver, independent of any loopback mode. PD0 goes High when less than three
zeros have been detected in any string of 2048 bits. PD0 returns Low when the
received signal contains more than three zeros in 2048 bits.
DO
If the QRSS function is enabled by the VCQE pin, PD0 remains High until pattern sync
is reached with the received signal. Once pattern lock is obtained, PD0 goes Low. The
sync/out-of-sync criteria is: less than 3/4 errors in 128 bits. After sync acquisition, bit
errors cause PD0 to go High for half a clock cycle. PD0 can be used to trigger an
external error counter.
15
21
RTIP0
AI Receive Tip and Ring - Port 0. These pins comprise the receive line interface and
should be connected to the line through a center-tapped 1:2 transformer. See Figure
16
22
RRING0
AI 14 through Figure 16 for details.
17 23
CLKE
Clock Edge Select. When CLKE is High, RPOS/RNEG or RDATA outputs are valid on
the falling edge of RCLK, and SDO is valid on the rising edge of SCLK.
DI
When CLKE is Low, RPOS/RNEG or RDATA outputs are valid on the rising edge of
RCLK, and SDO is valid on the falling edge of SCLK.
18
24
RRING1
AI Receive Tip and Ring - Port 1. These pins comprise the receive line interface and
should be connected to the line through a center-tapped 1:2 transformer. See Figure 14
19
25
RTIP1
AI through Figure 16 for details.
20 26
PD1
DO
Pattern Detect - Port 1. Reports AIS and QRSS pattern reception. See PD0 signal
description for details.
21 27
SDI
DI
Serial Data Input. Write data to the LXT332 registers is input on this pin. SDI is
sampled on the rising edge of SCLK.
22 28
PS1
DI
Port Select - Port 1. Selects the serial interface registers for port 1. For each read or
write operation, PS1 must transition from High to Low, and remain Low.
Transmit Tip and Ring - Port 1. These pins are differential driver outputs designed to
23 29 TRING1 AO drive a 35 - 200 Ω load. Line matching resistors and transformers can be selected to
26
32
TTIP1
AO give the desired pulse height. See Table 10 and Figure 14 through Figure 16 for
details.
24
30
TVCC1
S
+ 5 VDC - Port 1 Transmit Driver. TVCC1 must not vary from TVCC0 or VCC by more
than ± 0.3 V.
25
31
TGND1
S Ground - Port 1 Transmit Driver. Ground return for the TVCC1 power supply.
27 33
VCC
S +5 VDC. Power supply for all circuits except the transmit drivers.
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; S = Power
Supply.
Datasheet
11
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